S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 248

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S1D13503

Manufacturer Part Number
S1D13503
Description
S1d13503 Graphics Lcd Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Page 10
3.1 S1D13503 Default Setup
3.1.1 Configuration Options
3.1.2 Register Setting
S1D13503
X18A-G-003-05
The S1D13503 latches the state of the SRAM data bus during RESET to determine the power-on configuration. The chip
has internal pull-down resistors and therefore external pull-ups are only necessary when requiring a ’1’ state, see below.
1.
2.
3.
4.
5.
6.
Where 1 = pull-up with a 10K resistor; 0 = no pull-up resistor
All register settings are completely programmable and are dependent on display type, resolution, color and mode of
operation, see Functional Specification for details.
VD15 - VD13 = 101
VD12 - VD4 = 110000000
VD3 = 0
VD2 = 0
VD1 = 0
VD0 = 0
memory decoding for locations $A segment
I/O decoding for locations 1100000000b - 1100000001b
No byte swap of high and low bytes
ISA Bus interface, i.e. non- MC68K interface
Indexed I/O
8-bit bus interface
Epson Research and Development
ISA Bus Interface Considerations
Vancouver Design Center
Issue Date: 01/01/30

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