HM-6551 Intersil Corporation, HM-6551 Datasheet - Page 6

• Manufacturer Part Number: HM-6551
• Description: 256 X 4 Cmos Ram
• Manufacturer: Intersil Corporation

Timing Waveforms
The HM-6551/883 Read Cycle is initiated by the falling edge
of E. This signal latches the input address word and S2 into
on-chip registers providing the minimum setup and hold
times are met. After the required hold time, these inputs may
change state without affecting device operation. S2 acts as a
high order address and simplifies decoding. For the output to
be read, E, S1 must be low and W must be high. S2 must
have been latched low on the falling edge of E. The output
REFERENCE
REFERENCE
TIME
-1
0
1
2
3
4
5
TIME
S2
S1
W
D
E
Q
A
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E
H
H
L
L
HIGH
(8) TAVEL
(9) TS2LEL
(7) TEHEL
S1
H
H
X
L
L
L
X
-1
(3) TS1LQX
S2
X
X
X
X
X
L
L
INPUTS
0
VALID
TELS2X
TELAX
(11)
(10)
TAVQV (2)
FIGURE 1. READ CYCLE
TELQV (1)
W
X
H
H
H
H
X
H
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HM-6551/883
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TRUTH TABLE
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6-106
A
X
V
X
X
X
X
V
1
data will be valid at access time (TELQV). The HM-6551/883
has output data latches that are controlled by E. On the ris-
ing edge of E the present data is latched and remains in that
state until E falls. Also on the rising edge of E, S2 unlatches
and controls the outputs along with S1. Either or both S1 or
S2 may be used to force the output buffers into a high
impedance state.
TELEH (6)
D
X
X
X
X
X
X
X
2
(19) TELEL
VALID OUTPUT
OUTPUTS
Q
Z
Z
X
V
V
Z
Z
3
Memory Disabled
Addresses and S2 are Latched,
Cycle Begins
Output Enabled but Undefined
Data Output Valid
Outputs Latched, Valid Data,
S2 Unlatches
Prepare for Next Cycle
(Same as -1)
Cycle Ends, Next Cycle Begins
(Same as 0)
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(9) TS2LEL
(8) TAVEL
TEHEL (7)
FUNCTION
4
TS1HQZ (5)
5
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