HMP8115 Intersil Corporation, HMP8115 Datasheet - Page 29

• Manufacturer Part Number: HMP8115
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

NO.
NO.
BIT
BIT
2-1
2-1
7
6
5
4
3
0
7
6
5
4
3
0
Genlock Loss
Interrupt Mask
Input Signal Loss
Interrupt Mask
Closed Caption
Interrupt Mask
WSS
Interrupt Mask
Teletext
Interrupt Mask
Reserved
Vertical Sync
Interrupt Mask
Genlock Loss
Interrupt Status
Input Signal Loss
Interrupt Status
Closed Caption
Interrupt Status
WSS
Interrupt Status
Teletext
Interrupt Status
Reserved
Vertical Sync
Interrupt Status
FUNCTION
FUNCTION
If this bit is a “1”, an interrupt is generated when genlock is lost.
0 = Interrupt disabled
1 = Interrupt enabled
If this bit is a “1”, an interrupt is generated when a video signal is no longer detected on
the selected video input.
0 = Interrupt disabled
1 = Interrupt enabled
If this bit is a “1”, an interrupt is generated when the Caption_ODD_A and
Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain
new data.
0 = Interrupt disabled
1 = Interrupt enabled
If this bit is a “1”, an interrupt is generated when the WSS_ODD_A and WSS_ODD_B or
the WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
0 = Interrupt disabled
1 = Interrupt enabled
If this bit is a “1”, an interrupt is generated when teletext information is first detected at
the beginning of each field.
0 = Interrupt disabled
1 = Interrupt enabled
If this bit is a “1”, an interrupt is generated at the beginning of each field.
0 = Interrupt disabled
1 = Interrupt enabled
If this bit is a “1”, the reason for the interrupt request was that genlock was lost. To clear
the interrupt request, a “1” must be written to this bit.
If this bit is a “1”, the reason for the interrupt request was that the input video source is
no longer present. To clear the interrupt request, a “1” must be written to this bit.
If this bit is a “1”, the reason for the interrupt request was that the Caption_ODD_A and
Caption_ODD_B or the Caption_EVEN_A and Caption_EVEN_B data registers contain
new data. To clear the interrupt request, a “1” must be written to this bit.
If this bit is a “1”, the reason for the interrupt request was that the WSS_ODD_A and
WSS_ODD_B or the WSS_EVEN_A and WSS_EVEN_B data registers contain new da-
ta. To clear the interrupt request, a “1” must be written to this bit.
If this bit is a “1”, the reason for the interrupt request was that teletext data has been de-
tected in the current field. To clear the interrupt request, a “1” must be written to this bit.
If this bit is a “1”, the reason for the interrupt request was that a new field was started. To
clear the interrupt request, a “1” must be written to this bit.
TABLE 23. INTERRUPT STATUS REGISTER
TABLE 22. INTERRUPT MASK REGISTER
SUB ADDRESS = 0F
SUB ADDRESS = 10
HMP8115
29
DESCRIPTION
DESCRIPTION
H
H
RESET
RESET
STATE
STATE
00
00
0
0
0
0
0
0
0
0
0
0
0
0
B
B
B
B
B
B
B
B
B
B
B
B
B
B