HMP8115 Intersil Corporation, HMP8115 Datasheet - Page 6

• Manufacturer Part Number: HMP8115
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

which sets the DC offset level into the input video amplifier.
During the S-video mode of operation the capacitor on the
C_CAP pin performs the same function as the L_CAP
capacitor, except the chroma video amplifier’s DC offset is
set so that the chroma A/D generates a code of 128 during
the back porch. The internal timing windows for AGC and DC
Restoration are show in Figure 3.
INPUT SIGNAL DETECTION
It is assumed there is no video input if a horizontal sync is
not detected for 16 consecutive lines. When no video has
been detected, nominal video timing is generated for the
previously detected or programmed standard. A maskable
interrupt is included to flag when no video has been detected
(bit 6 of the INTERRUPT MASK register 0F
blue/black/color bar output modes to be enabled if desired.
The vertical sync interrupt can be used in determining when
a video signal is present at the currently selected video mux
input. Bit 0 of register 0F
interrupts.
VERTICAL SYNC AND FIELD DETECTION
The vertical sync and field detect circuit uses a low time
counter to detect the vertical sync sequence in the video
data stream. The low time counter accumulates the low time
encountered during any sync pulse, including serration and
equalization pulses. When the low time count exceeds the
vertical sync detect threshold, VSYNC is asserted immedi-
ately. FIELD is asserted at the same time that VSYNC is
asserted. FIELD is asserted low for odd fields and high for
even fields. Field is determined from the location in the video
line where VSYNC is detected. If VSYNC is detected in the
first half of the line, the field is odd. If VSYNC is detected in
the second half of a line, the field is even.
In the case of lost vertical sync or excessive noise that would
prevent the detection of vertical sync, the FIELD output will
continue to toggle. Lost vertical sync is declared if after 337
lines, a vertical sync period was not detected for 1 or 3
(selectable) successive fields as specified by bit 2 of the
GENLOCK CONTROL register 04
PLLs are initialized to the acquisition state.
DC RESTORE
FIGURE 3. AGC AND DC RESTORE INTERNAL TIMING
VIDEO INPUT
AGC
H
is used to enable vertical sync
H
. When this occurs, the
H
) allowing for
HMP8115
6
Y/C SEPARATION
A composite video signal has the luma (Y) and chroma (C)
information mixed in the same video signal. The Y/C separa-
tion process is responsible for separating the composite
video signal into these two components. The HMP8115 uti-
lizes a comb filter to minimize the artifacts that are associ-
ated with the Y/C separation process.
INPUT SAMPLE RATE CONVERTER
The input sample rate converter is used to convert video
data sampled at the CLK2 rate to a virtual 4xf
for comb filtering and color demodulation. An interpolating
filter is used to generate the 4xf
Figure 4.
COMB FILTER
A 2-line comb filter, using a single line delay, is used to per-
form part of the Y/C separation process. During S-video
operation, the Y signal bypasses the comb filter; the C signal
is processed by the comb filter since it is an integral part of
the chroma demodulator. During PAL operation, the chroma
trap filter should also be enabled for improved performance.
Since a single line store is used, the chroma will normally
have a half-line vertical offset from the luma data. This may
be eliminated, vertically aligning the chroma and luma sam-
ples, at the expense of vertical resolution of the luma. Bit 0 of
the OUTPUT FORMAT register 02
CHROMA DEMODULATION
The output of the comb filter is further processed using a
patented frequency domain transform to complete the Y/C
separation and demodulate the chromanance.
Demodulation is done at a virtual 4xf
the interpolated data samples to generate U and V data. The
demodulation process decimates by 2 the U/V sample rate.
OUTPUT SAMPLE RATE CONVERTER
The output sample rate converter converts the Y, U and V
data from a virtual 4xf
sample rate (i.e., 13.5MHz). It also vertically aligns the sam-
ples based on the horizontal sync information embedded in
the digital video data stream. The output sample rate is
determined by the selected video standard and whether
FIGURE 4. SAMPLE RATE CONVERSION
INCOMING VIDEO SAMPLES
4xf
RESAMPLED VIDEO
SC
SC
sample rate to the desired output
SC
H
samples as illustrated in
controls this option.
SC
sample rate using
SC
TIME
TIME
sample rate