HMP8156 Intersil Corporation, HMP8156 Datasheet - Page 15

• Manufacturer Part Number: HMP8156
• Description: Ntsc/pal Encoder
• Manufacturer: Intersil Corporation

The analog RGB outputs have a range of 0.3-1.0V with no
blanking pedestal. Composite sync information (0.0-0.3V)
may be optionally added to the green output. Closed cap-
tioning data is not included on the RGB outputs.
The HMP8156 also generates composite video when in
RGB output mode. The analog composite video is output
onto the NTSC/PAL 1 pin. Red information is output onto the
NTSC/PAL 2 pin, blue information is output onto the C pin,
and green information is output onto the Y pin. All four out-
puts are time aligned.
Power Down Mode
When the power down mode is enabled, all of the DACs are
powered down (forcing their outputs to zero) and most of the
internal clocks are stopped. The host processor may still
read from and write to the internal control registers.
DATA WRITE
DATA READ
SDA
SCL
S
S
0100 000 OR
CHIP ADDR
CHIP ADDR
0100 0010
0x40 OR
0x42
CONDITION
START
S
A
A
SUB ADDR
SUB ADDR
ADDRESS
FIGURE 16. REGISTER WRITE PROGRAMMING FLOW
1-7
A
A
FIGURE 15. I
REGISTER
SUBADDR
S
POINTED
TO BY
DATA
R/W
8
CHIP ADDR
0x41 OR
0x43
HMP8156
2
A
MAY BE REPEATED
C SERIAL TIMING FLOW
OPTIONAL FRAME
ACK
9
15
DATA
n TIMES
A
Host Interfaces
Reset
The HMP8156 resets to its default operating mode on power
up, when the reset pin is asserted for at least four CLK
cycles, or when the software reset bit of the host control reg-
ister is set. During the reset cycle, the encoder returns its
internal registers to their reset state and deactivates the I
interface.
I
The HMP8156 provides a standard I
ports fast-mode (up to 400 KBPS) transfers. The device acts
as a slave for receiving and transmitting data only. It will not
respond to general calls or initiate a transfer. The encoder’s
slave address is either 0100 000x
low or 0100 001x
is the I
The I
the interface is not active, SCL and SDA must be pulled high
using external 4-6k
data timing is shown in Figures 15 and 16.
2
C Interface
REGISTER
SUBADDR
POINTED
DATA
TO BY
2
C interface consists of the SDA and SCL pins. When
A
2
C read flag.)
1-7
P
DATA
A
MAY BE REPEATED
OPTIONAL FRAME
B
DATA
when it is high. (The ‘x’ bit in the address
n TIMES
8
pull-up resistors. The I
NA
ACK
P
9
B
when the SA input pin is
2
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
C interface and sup-
CONDITION
STOP
FROM MASTER
FROM HMP8156
P
2
C clock and
2
C