HMP8156 Intersil Corporation, HMP8156 Datasheet - Page 16

• Manufacturer Part Number: HMP8156
• Description: Ntsc/pal Encoder
• Manufacturer: Intersil Corporation

During I
address specifies the sub address, and is written into the
address register. Only the seven LSBs of the subaddress are
used; the MSB is ignored. Any remaining data bytes in the
I
with the register specified by the address register. The 7-bit
address register is incremented after each data byte in the
I
or reserved registers is ignored.
During I
fied by the address register is output. The address register is
incremented after each data byte in the I
Reserved bits within registers return a value of “0”. Reserved
registers return a value of 00
The HMP8156’s operating modes are determined by the
contents of its internal registers which are accessed via the
I
the host processor at any time. However, some of the bits
and words are read only or reserved and data written to
these bits is ignored.
Table 9 lists the HMP8156’s internal registers. Their bit
descriptions are listed in Tables 10-27.
2
2
2
NUMBER
NUMBER
C write cycle are written to the control registers, beginning
C write cycle. Data written to reserved bits within registers
C interface. All internal registers may be written or read by
BIT
BIT
7-0
7-5
4-3
2-0
2
2
C read cycles, data from the control register speci-
C write cycles, the first data byte after the slave
Product ID
Video Timing
Standard
Output Format
Reserved
FUNCTION
FUNCTION
H
.
This 8-bit register specifies the last two digits of the product number. It is a read-only
register. Data written to it is ignored.
000 = (M) NTSC
001 = (M) NTSC with a 0 IRE setup; also called (NSM) NTSC
010 = (B, D, G, H, I) PAL
011 = (M) PAL
100 = (N) PAL
101 = combination (N) PAL; also called (CN) PAL
110 = reserved
111 = reserved
These bits must be set to “00” during (M, NSM) NTSC and (M, N, CN) PAL modes.
00 = Composite + Y/C
01 = reserved
10 = Composite + RGB (no sync on green)
11 = Composite + RGB (with sync on green)
TABLE 11. OUTPUT FORMAT REGISTER
2
TABLE 10. PRODUCT ID REGISTER
C read cycle.
SUB ADDRESS = 00
SUB ADDRESS = 01
HMP8156
16
DESCRIPTION
DESCRIPTION
SUB ADDRESS
(HEX)
07-0E
14-1F
26-2F
30-7F
H
H
0F
00
01
02
03
04
05
06
10
11
12
13
20
21
22
23
24
25
TABLE 9. CONTROL REGISTER NAMES
CONTROL REGISTER
Closed Caption_284A
Closed Caption_284B
Closed Caption_21A
Closed Caption_21B
Start H_Blank High
Start V_Blank High
Start H_Blank Low
Start V_Blank Low
Video Processing
Aux Data Enable
Test and Unused
Output Format
End H_Blank
End V_Blank
Input Format
Host Control
Timing I/O 1
Timing I/O 2
Product ID
Reserved
Reserved
Reserved
CONDITION
RESET
RESET
RESET
STATE
STATE
56
00
06
A0
00
00
00
18
80
80
80
80
4A
03
7A
03
01
13
000
000
56
00
-
-
-
-
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
B
B
B