HMP8156 Intersil Corporation, HMP8156 Datasheet - Page 21

• Manufacturer Part Number: HMP8156
• Description: Ntsc/pal Encoder
• Manufacturer: Intersil Corporation

NUMBER
NUMBER
NUMBER
BIT
BIT
BIT
7-0
7-1
7-0
0
Assert BLANK
Output Signal
(Vertical)
Reserved
Assert BLANK
Output Signal
(Vertical)
Negate BLANK
Output Signal
(Vertical)
FUNCTION
FUNCTION
FUNCTION
This 8-bit register is cascaded with Start V_Blank High Register to form a 9-bit
start_vertical_blank register. During normal operation, it specifies the line number (n) to
start ignoring pixel input data (and what line number to start blanking the output video)
each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start ignoring
pixel input data each noninterlaced input frame. The output video will be blanked starting
on line number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
not follow standard NTSC or PAL line numbering). This register is ignored unless BLANK
is configured as an output.
This 1-bit register is cascaded with Start V_Blank Low Register to form a 9-bit
start_vertical_blank register. This register is ignored unless BLANK is configured as an
output.
During normal operation, this 8-bit register specifies the line number (n) to start inputting
pixel input data (and what line number to start generating active output video) each odd
field; for even fields, it occurs on line (n + 262) or (n + 313).
During SIF input mode, the register value (n) specifies the line number to start inputting
pixel input data each noninterlaced input frame. The output video will be active starting
on line number (n) each odd field; for even fields, it occurs on line (n + 262) or (n + 313).
The leading edge of VSYNC at the start of an odd field is count 000
not follow standard NTSC or PAL line numbering). This register is ignored unless BLANK
is configured as an output.
TABLE 26. START V_BLANK HIGH REGISTER
TABLE 25. START V_BLANK LOW REGISTER
TABLE 27. END V_BLANK REGISTER
SUB ADDRESS = 23
SUB ADDRESS = 24
SUB ADDRESS = 25
HMP8156
21
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
H
(note that this does
(note that this does
0000000
RESET
STATE
RESET
STATE
RESET
STATE
03
13
1
B
H
H
B