HMP8116 Intersil Corporation, HMP8116 Datasheet - Page 13

• Manufacturer Part Number: HMP8116
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

If DVLD_LTC=1 and DVLD_DCYC=1, DVALID is present
during the entire line time on all scan lines. DVALID is
asserted during the blanking intervals as needed to ensure a
constant number of total samples per line. The timing for this
mode differs from the timing shown in figures 13 and 14 only
in that DVALID will also be asserted during the blanking por-
tion of the video line time as described above.
If 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB data is gen-
erated, it is output following the rising edge of CLK2 while
NOTES:
12. Y
13. BLANK is asserted per Figure 8.
NOTE:
14. BLANK is asserted per Figure 8.
DVALID
BLANK
P15-P8
[P14-P10]
P7-P0
CLK
every cycle due to the 4:2:2 subsampling.
P15-P11
[P9-P5]
DVALID
P10-P5
0
P4-P0
is the first active luminance pixel data of a line. Cb
CLK
FIGURE 12. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)
t
DVLD
FIGURE 11. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)
t
DVLD
Cb
Y
0
0
G
B
R
0
0
0
Cr
Y
0
1
G
B
R
1
1
1
0
and Cr
HMP8116
0
are first active chrominance pixel data in a line. Cb and Cr will alternate
13
DVALID is asserted. Either linear or gamma-corrected RGB
data may be output. The pixel output timing is shown in Fig-
ures 11 to 14.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr; the RGB out-
puts have a value of 0.
Cb
Y
2
2
G
B
R
2
2
2
Cr
Y
2
3
G
B
R
3
3
3
Cb
Y
4
4
G
B
R
4
4
4