HMP8116 Intersil Corporation, HMP8116 Datasheet - Page 34

• Manufacturer Part Number: HMP8116
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

15-8
NO.
NO.
NO.
NO.
BIT
BIT
BIT
BIT
7-6
5-0
1-0
7-0
7
6
5
4
3
2
Reserved
Sharpness
Adjust
Software Reset
Power Down
Closed Caption
Odd Field
Read Status
Closed Caption
Even Field
Read Status
WSS
Odd Field
Read Status
WSS
Even Field
Read Status
Reserved
Odd Field
Caption Data
Odd Field
Caption Data
FUNCTION
FUNCTION
FUNCTION
FUNCTION
These bits control the amount of gain control of high frequency luminance signals (either
2.6MHz or Fsc). They may have a value of +12dB (“11 1111”) to -12dB (“00 0100”). A val-
ue of 0dB (“01 0000”) has no effect on the data. This register is ignored if the sharpness
mode selection is “disable sharpness control” or “reserved”.
When this bit is set to 1, the entire device except the I
exactly like the RESET input going active. The software reset will initialize all register bits
to their reset state. Once set this bit is self clearing. This bit is cleared on power-up by the
external RESET pin.
When this bit is set to a 1, the entire device is shut down except the I
the clock. For normal decoding operations this bit should be set to a 0.
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption
data has been read out via the I
0 = No new caption data
1 = Caption_ODD_A and Caption_ODD_B data registers contain new data.
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the caption
data has been read out via the I
0 = No new caption data
1 = Caption_EVEN_A and Caption_EVEN_B data registers contain new data.
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS
data has been read out via the I
0 = No new WSS data
1 = WSS_ODD_A and WSS_ODD_B data registers contain new data.
This bit is read-only. Data written to this bit is ignored. The bit is cleared when the WSS
data has been read out via the I
0 = No new WSS data
1 = WSS_EVEN_A and WSS_EVEN_B data registers contain new data.
If odd field captioning is enabled and present, this register is loaded with the first eight bits
of caption data on line 18, 21, or 22. Bit 0 corresponds to the first bit of caption information.
Data written to this register is ignored.
If odd field captioning is enabled and present, this register is loaded with the second eight
bits of caption data on line 18, 21, or 22. Data written to this register is ignored.
TABLE 39. CLOSED CAPTION_ODD_A DATA REGISTER
TABLE 40. CLOSED CAPTION_ODD_B DATA REGISTER
TABLE 38. HOST CONTROL REGISTER
TABLE 37. SHARPNESS REGISTER
SUB ADDRESS = 1E
SUB ADDRESS = 1F
SUB ADDRESS = 20
SUB ADDRESS = 21
HMP8116
2
2
2
2
34
C interface or as BT.656 ancillary data.
C interface or as BT.656 ancillary data.
C interface or as BT.656 ancillary data.
C interface or as BT.656 ancillary data.
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
H
H
H
H
2
C bus is reset to a known state
2
C bus by gating off
010000
RESET
RESET
RESET
RESET
STATE
STATE
STATE
STATE
00
00
80
80
0
0
0
0
0
0
B
B
B
B
B
B
B
H
H
B
B