IDT72261LA20PF IDT, Integrated Device Technology Inc, IDT72261LA20PF Datasheet - Page 22

• Manufacturer Part Number: IDT72261LA20PF
• Description: IC FIFO 8192X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72261LA20PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 12ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 75mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72261LA20PF

NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
D
Q
WCLK
RCLK
NOTE:
1. OE = LOW
IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
WCLK
WEN
0
REN
RCLK
0
PAF
In IDT Standard mode: D = 16,384 for the IDT72261LA and 32,768 for the IDT72271LA.
In FWFT mode: D = 16,385 for the IDT72261LA and 32,769 for the IDT72271LA.
rising edge of RCLK and the rising edge of WCLK is less than t
WEN
SKEW2
- Q
REN
- D
LD
LD
7
7
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKH
t
CLKH
t
CLKH
PAE OFFSET
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
(LSB)
DATA IN OUTPUT
t
t
CLK
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENS
t
t
ENS
CLK
t
REGISTER
t
LDS
DS
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
t
CLKL
t
ENS
LDS
t
CLKL
D - (m+1) words in FIFO
t
CLKL
t
ENH
PAE OFFSET
t
t
t
ENH
DH
LDH
t
LDH
t
t
ENH
A
(MSB)
1
(2)
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
PAE OFFSET
(LSB)
PAF OFFSET
2
(LSB)
22
t
PAF
t
ENS
t
SKEW2
PAE OFFSET
(MSB)
(3)
PAF OFFSET
(MSB)
t
ENH
D - m words in FIFO
1
t
t
LDH
ENH
PAF OFFSET
COMMERCIAL AND INDUSTRIAL
t
DH
(LSB)
(2)
t
t
ENH
LDH
t
A
TEMPERATURE RANGES
PAF
2
). If the time between the
t
PAF
JANUARY 7, 2009
PAF OFFSET
D-(m+1) words
in FIFO
4671 drw 19
(MSB)
4671 drw 17
4671 drw 18
(2)