IDT72261LA20PF IDT, Integrated Device Technology Inc, IDT72261LA20PF Datasheet - Page 24

• Manufacturer Part Number: IDT72261LA20PF
• Description: IC FIFO 8192X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72261LA20PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 12ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 75mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72261LA20PF

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the
IR and OR functions in FWFT mode. Because of variations in skew between
RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR assertion
to vary by one cycle between FIFOs. In IDT Standard mode, such problems
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
MASTER RESET (MRS)
PARTIAL RESET (PRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 19. Block Diagram of 16,384 x 18 and 32,768 x 18 Width Expansion
D
0
- Dm
LOAD (LD)
m
#1
72261LA
72271LA
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
24
0
n
- Qm
can be avoided by creating composite flags, that is, ANDing EF of every FIFO,
and separately ANDing FF of every FIFO. In FWFT mode, composite flags
can be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
72271LA devices. D
Q
be attained by adding additional IDT72261LA/72271LA devices.
0
Figure 21 demonstrates a width expansion using two IDT72261LA/
-Q
72261LA
72271LA
8
FIFO
from each device form a 18-bit wide output bus. Any word width can
IDT
#2
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
0
Qm
- D
+1
8
from each device form a 18-bit wide input bus and
- Qn
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
JANUARY 7, 2009
4671 drw 22
GATE
(1)