IDT72261LA20PF IDT, Integrated Device Technology Inc, IDT72261LA20PF Datasheet - Page 9

• Manufacturer Part Number: IDT72261LA20PF
• Description: IC FIFO 8192X18 LP 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72261LA20PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 50MHz
• Access Time: 20ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 12ns
• Word Size: 9b
• Organization: 16Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 75mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72261LA20PF

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
LD
0
0
0
X
1
1
1
8
8
8
8
WEN
X
0
1
1
1
0
1
IDT72261LA ⎯ 16,384 x 9 ⎯ BIT
5
5
7
7
3FFH if LD is HIGH at Master Reset
3FFH if LD is HIGH at Master Reset
07FH if LD is LOW at Master Reset
07FH if LD is LOW at Master Reset
REN
EMPTY OFFSET (MSB) REG.
EMPTY OFFSET (LSB) REG.
X
1
0
1
1
0
1
FULL OFFSET (LSB) REG.
FULL OFFSET (MSB) REG.
Figure 4. Programmable Flag Offset Programming Sequence
DEFAULT VALUE
DEFAULT VALUE
Figure 3. Offset Register Location and Default Values
00H
00H
SEN
X
1
1
1
X
X
0
WCLK
0
0
0
X
X
X
X
0
9
8
8
8
8
RCLK
IDT72271LA ⎯ 32,768 x 9 ⎯ BIT
X
X
X
X
X
6
6
7
7
3FFH if LD is HIGH at Master Reset
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
07FH if LD is LOW at Master Reset
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
28 bits for the 72261LA
30 bits for the 72271LA
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
Write Memory
Read Memory
No Operation
EMPTY OFFSET (MSB) REG.
EMPTY OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
FULL OFFSET (MSB) REG.
DEFAULT VALUE
DEFAULT VALUE
00H
00H
COMMERCIAL AND INDUSTRIAL
Selection
TEMPERATURE RANGES
4671 drw 06
JANUARY 7, 2009
0
0
0
0
4671 drw 07