MT29F1G08ABBHC-ET Micron, MT29F1G08ABBHC-ET Datasheet - Page 17

• Manufacturer Part Number: MT29F1G08ABBHC-ET
• Description: NAND Flash Memory; Density: 1Gb; Organization: 128Mbx8; Bits/Cell: SLC; I/O: Common; Supply Voltage: 1.8V; Operating Temperature Range: -40° to +85°C; Package: 63-VFBGA
• Manufacturer: Micron

Data Input
READ
READY/BUSY#
PDF: 09005aef81dc05df / Source: 09005aef821d5f08
1gb_nand_m48a__2.fm - Rev. E 1/08 EN
RANDOM DATA INPUT and OUTPUT commands need only column addresses, so only 2
address cycles are required. Refer to the command descriptions to determine the
addressing requirements for each command.
Data is written to the data register on the rising edge of WE# when these conditions are
met:
• CE#, CLE, and ALE are LOW
• the device is not busy
Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure 46 on
page 57 for additional data input details.
After a READ command is issued, data is transferred from the memory array to the data
register on the rising edge of WE#. R/B# goes LOW for
transfer is complete. When data is available in the data register, it is clocked out of the
part by RE# going LOW (see Figure 12 on page 21 for timing details).
The READ STATUS (70h) command or the READY/BUSY signal can be used to determine
when the device is ready (see the READ STATUS command section starting on page 28
for details).
The R/B# output provides a hardware method of indicating the completion of a PRO-
GRAM/ERASE/READ operation. The signal is typically HIGH, and transitions to LOW
after the appropriate command is written to the device. The signal’s open-drain driver
enables multiple R/B# outputs to be OR-tied. The signal requires a pull-up resistor for
proper operation. The READ STATUS command can be used in place of R/B#. Typically,
R/B# would be connected to an interrupt ball on the system controller (see Figure 8 on
page 18).
The combination of Rp and the capacitive loading of the R/B# circuit determine the
R/B# rise time. The actual value used for Rp depends on the system timing require-
ments. Large Rp values delay R/B# significantly. At the 10 percent/90 percent points on
the R/B# waveform, rise time is approximately two time constants (TC).
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The R/B# fall time is determined mainly by the output impedance of R/B# and the total
load capacitance. Refer to Figures 9 and 10 on page 18, which depict approximate Rp
values using a circuit load of 100pF.
The minimum value for Rp is determined by the R/B# output drive capability, the output
voltage swing, and V
Where ΣI
Rp MIN, 1.8V part
(
L
is the sum of the input currents of all devices tied to the R/B# pin.
CC
.
)
=
V
---------------------------------------------------------------
TC
CC
17
(
=
MAX
I
R
OL
×
) V
C
+
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ΣI
OL
L
1Gb: x8, x16 NAND Flash Memory
(
MAX
)
=
-------------------------- -
3mA
t
R and transitions HIGH after the
1.85V
+
ΣI
©2006 Micron Technology, Inc. All rights reserved.
L
Bus Operation