CS493002-CL Cirrus Logic, CS493002-CL Datasheet - Page 18

• Manufacturer Part Number: CS493002-CL
• Description: Multi-Standard Audio Decoder Family
• Manufacturer: Cirrus Logic

1.12. Switching Characteristics — CMPDAT, CMPCLK
(T
1.13. Switching Characteristics — Parallel Data Input
(T
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
18
Serial compressed data clock CMPCLK period
CMPDAT setup before CMPCLK high
CMPDAT hold after CMPCLK high
CMPCLK Period
DATA[7:0] setup before CMPCLK high
DATA[7:0] hold after CMPCLK high
A
A
= 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
= 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/4 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLK == 100ns
DCLK == 65 MHz after boot, i.e. DCLK == 15.4ns
It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.
D A T A [7:0]
C M P C LK
CM P DA T
CM P CL K
Figure 11. Parallel Data Timing (when not in a parallel control mode)
Parameter
Parameter
Figure 10. Serial Compressed Data Timing
T
cm psu
T
cm ps u
T
cm pclk
T
cm p clk
Symbol
T
T
T
cmpclk
Symbol
cmpsu
cmphld
T
T
T
cmpclk
cmpsu
cmphld
T
cm phld
T
cm p hld
4*DCLK + 10
CS49300 Family DSP
L
L
Min
Min
10
10
= 20 pF)
= 20 pF)
5
3
-
Max
Max
27
-
-
DS339PP4
Unit
ns
ns
ns
MHz
Unit
ns
ns