CS493002-CL Cirrus Logic, CS493002-CL Datasheet - Page 33

• Manufacturer Part Number: CS493002-CL
• Description: Multi-Standard Audio Decoder Family
• Manufacturer: Cirrus Logic

Only the subsection describing the communication
mode being used needs to be read by the system
designer.
6.1. Serial Communication
The CS493XX has a serial control port that
supports
communication.
The
communication mode in more detail. Flow
diagrams will illustrate read and write cycles.
Timing diagrams will be shown to demonstrate
relative edge positions of signal transitions for read
and write operations.
6.1.1. SPI Communication
SPI communication with the CS493XX is
accomplished with 5 communication lines: chip
select, serial control clock, serial data in, serial data
out and an interrupt request line to signal that the
DSP has data to transmit to the host.
the mnemonic, pin name, and pin number of each
of these signals on the CS493XX.
6.1.1.1.Writing in SPI
When writing to the device in SPI the same
protocol will be used whether writing a byte, a
message or even an entire executable download
image. The examples shown in this document can
be expanded to fit any write situation.
"SPI Write Flow Diagram" on page 33
typical write sequence:
The following is a detailed description of an SPI
write sequence with the CS493XX.
DS339PP4
Interrupt Request
Serial Data Out
Serial Data In
Serial Clock
Chip Select
Mnemonic
following
Table 3. SPI Communication Signals
both
SPI
sections will
Pin Name
SCDOUT
INTREQ
SCCLK
SCDIN
and
CS
I
2
C
®
explain
Table 3
Pin Number
forms
Figure 19,
18
19
20
7
6
shows a
shows
each
of
1) An SPI transfer is initiated when chip select
2) This is followed by a 7-bit address and the
3) The host should then clock data into the device
4) When all of the bytes have been transferred,
(CS) is driven low.
read/write bit set low for a write. The address
for the CS493XX defaults to 0000000b. It is
necessary to clock this address in prior to any
transfer in order for the CS493XX to accept the
write. In other words a byte of 0x00 should be
clocked into the device preceding any write.
The 0x00 byte represents the 7 bit address
0000000b, and the least significant bit set to 0
to designate a write.
most significant bit first, one byte at a time. The
data byte is transferred to the DSP on the falling
edge of the eighth serial clock. For this reason,
the serial clock should be default low so that
eight transitions from low to high to low will
occur for each byte.
chip select should be raised to signify an end of
Figure 19. SPI Write Flow Diagram
WRITE ADDRESS BYTE
SET TO 0 FOR WRITE
SPI START: CS (LOW)
SEND DATABYTE
CS49300 Family DSP
WITH MODE BIT
MORE DATA?
CS (HIGH)
N
Y
33