CS493002-CL Cirrus Logic, CS493002-CL Datasheet - Page 58

• Manufacturer Part Number: CS493002-CL
• Description: Multi-Standard Audio Decoder Family
• Manufacturer: Cirrus Logic

58
WRITE_*(HW_CONFIG_MSG,
WRITE_*(SW_CONFIG_MSG,
RESET(LOW)
ABOOT(LOW)
AUTOBOOT COMPLETE
WAIT 200 MS
RESET(HIGH)
WRITE_*(KICKSTART,
CORRECT VALUE?
READ_*(VARIABLE)
RELEASE ABOOT
(NOTE 4)
(NOTE 4)
(NOTE 4)
(NOTE 4)
HW_MSG_SIZE)
SW_MSG_SIZE)
MSG_SIZE)
Y
(NOTE 1)
(NOTE 3)
(NOTE 2)
N
Figure 36. Autoboot Sequence
WAIT 5 MS
Notes: 1. RESET must be held LOWT
2. The RD and WR pins must be configured to select a
3. INTREQ should be ignored during this period. 200 ms
4. The READ_* and WRITE_* functions are
serial communication mode as defined in the
CS493XX Datasheet. The setup (T
(T
AUTOBOOT pins.
is typical but this time is application code specific and
may be higher. Wait times should be verified by the
designer.
placeholders for the READ_I2C/READ_SPI and
WRITE_I2C/WRITE_SPI functions defined in
6.1, “Serial Communication” on page
rsthld
) times must be observed for the RD, WR, and
CS49300 Family DSP
rstl
.
rstsu
33.
) and hold
Section
DS339PP4