MCM63F733A Motorola, MCM63F733A Datasheet

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MCM63F733A

Manufacturer Part Number
MCM63F733A
Description
128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
128K x 32 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
vide a burstable, high performance, secondary cache for the PowerPC
other high performance microprocessors. It is organized as 128K words of 32
bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, a 2–bit address counter, and high speed
SRAM onto a single monolithic circuit for reduced parts count in cache data
RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K). CMOS circuitry reduces the overall power con-
sumption of the integrated functions for greater reliability.
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
addresses can be generated internally by the MCM63F733A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO) and con-
trolled by the burst address advance (ADV) input pin.
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
from the memory array.
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC
Standard JESD8–5 compatible.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MOTOROLA FAST SRAM
REV 2
3/20/98
Motorola, Inc. 1998
The MCM63F733A is a 4M–bit synchronous fast static RAM designed to pro-
Addresses (SA), data inputs (DQx), and all control signals except output
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
Write cycles are internally self–timed and are initiated by the rising edge of the
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
For read cycles, a flow–through SRAM allows output data to simply flow freely
The MCM63F733A operates from a 3.3 V core power supply and all outputs
MCM63F733A–10 = 10 ns Access/13 ns Cycle (75 MHz)
MCM63F733A–11 = 11 ns Access/15 ns Cycle (66 MHz)
3.3 V + 10% / – 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
Single–Cycle Deselect
Sleep Mode (ZZ)
100–Pin TQFP Package
and
MCM63F733A
Order this document
by MCM63F733A/D
CASE 983A–01
TQ PACKAGE
MCM63F733A
TQFP
1

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MCM63F733A Summary of contents

Page 1

... For read cycles, a flow–through SRAM allows output data to simply flow freely from the memory array. The MCM63F733A operates from a 3.3 V core power supply and all outputs operate 3.3 V power supply. All inputs and outputs are JEDEC Standard JESD8–5 compatible. ...

Page 2

... LBO ADV K ADSC ADSP SA SA1 SA0 SGW SW SBa SBb SBc SBd SE1 SE2 SE3 G MCM63F733A 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 17 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b WRITE REGISTER c WRITE REGISTER d K2 ENABLE REGISTER 2 17 128K x 32 ARRAY DATA–IN ...

Page 3

... NC 79 DQb 78 DQb V DDQ DQb DQb 74 73 DQb 72 DQb DDQ 69 DQb 68 DQb DQa 63 62 DQa 61 V DDQ DQa 58 DQa 57 DQa 56 DQa DDQ 54 53 DQa 52 DQa MCM63F733A 3 ...

Page 4

... MCM63F733A 4 Symbol Type ADSC Input Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. ...

Page 5

... READ X X High–Z WRITE 0 X High–Z WRITE 0 X High–Z WRITE 1 X High–Z WRITE 1 X High–Z WRITE I/O Status Data Out (DQx) High–Z High–Z High–Z High–Z 4th Address (Internal X11 X00 X01 X10 MCM63F733A 5 ...

Page 6

... Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1). MCM63F733A 6 (LBO = 3rd Address (Internal) X ...

Page 7

... KHKH (MIN) Figure 1. Undershoot Voltage Min Typ Max Unit 3.135 3.3 3.6 V 2.375 2.5 2.9 V – 0.3 — 0.7 V 1.7 — 0.3 V 1.7 — V DDQ + 0.3 V — — 0.7 V 1.7 — — V Min Typ Max Unit 3.135 3.3 3.6 V 3.135 3 – 0.5 — 0 — 0 — V DDQ + 0.5 V — — 0.4 V 2.4 — — V MCM63F733A 7 ...

Page 8

... MCM63F733A–10 I DDA — MCM63F733A–11 I SB2 — — I SB3 — MCM63F733A–10 I SB4 — MCM63F733A–11 MCM63F733A–10 I SB5 — MCM63F733A– DDQ – 0.2 V. CMOS levels for other inputs are Symbol I/O Typ Max ...

Page 9

... See Figure 2 Unless Otherwise Noted MCM63F733A–11 66 MHz U i Unit Notes N Min Max 15 — — — ns — — 3 — 1.5 — — — 3 1.5 3 — ns 0.5 — ns — KHKH 2 x — KHKH — MCM63F733A 9 ...

Page 10

... OUTPUT Figure 3. Lumped Capacitive Load and Typical Derating Curve MCM63F733A 10 OUTPUT 1.25 V Figure 2. AC Test Load 2400 2200 2000 1800 1600 1400 1200 C L 1000 800 600 400 200 LUMPED CAPACITANCE (pF 100 MOTOROLA FAST SRAM ...

Page 11

... Pull–Up for V DDQ = 2.5 V 3.6 3.135 2.8 – 120 – 120 1.65 – 120 – 108 1.4 – 81 – (b) Pull–Up: V DDQ = (c) Pull–Down – 40 – 105 CURRENT (mA) – 40 – 80 – 120 CURRENT (mA CURRENT (mA) MCM63F733A 11 ...

Page 12

... MCM63F733A 12 MOTOROLA FAST SRAM ...

Page 13

... MCM63F733A 13 ...

Page 14

... SLEEP MODE A sleep mode feature, the ZZ pin, has been implemented on the MCM63F733A. It allows the system designer to place the RAM in the lowest possible power condition by asserting ZZ. The sleep mode timing diagram shows the different modes of operation: Normal Operation, No READ/WRITE Allowed, and Sleep Mode. Each mode has its own set of constraints and conditions that are allowed ...

Page 15

... REF S 0.20 ––– 0.008 ––– R1 0.08 ––– 0.003 ––– R2 0.08 0.20 0.003 0.008 ––– 0 ––– MCM63F733A 15 ...

Page 16

... Motorola, Inc. Motorola, Inc Equal Mfax is a trademark of Motorola, Inc. JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, CUSTOMER FOCUS CENTER: 1-800-521-6274 MOTOROLA FAST SRAM MCM63F733A/D ...

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