MCM63F733A Motorola, MCM63F733A Datasheet - Page 9

• Manufacturer Part Number: MCM63F733A
• Description: 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
• Manufacturer: Motorola

Input Timing Measurement Reference Level
Input Pulse Levels
Input Rise/Fall Time
NOTES:
MOTOROLA FAST SRAM
READ/WRITE CYCLE TIMING
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
Setup Times:
Hold Times:
Sleep Mode Standby
Sleep Mode Recovery
Sleep Mode High to Q High–Z
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
5. This parameter is sampled and not 100% tested.
6. Measured at
or ADSC is asserted.
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at V DDQ /2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P
Parameter
200 mV from steady state.
. . . . . . . . . . . . . . . . . . . . . .
(V DD = 3.3 V + 10%, – 5%, T A = 0 to 70 C, Unless Otherwise Noted)
ADSP, ADSC, ADV
ADSP, ADSC, ADV
AC OPERATING CONDITIONS AND CHARACTERISTICS
(See Notes 1 through 4)
Chip Enable
Chip Enable
Address
Address
Data In
Data In
. . . . . . . . . . . . . .
Write
Write
1.0 V/ns (20 to 80%)
t KHADSX
S
Symbol
t KHQX1
t KHQX2
t ADSKH
t ZZREC
t WVKH
t KHWX
t KHQV
t GHQZ
t KHKH
t GLQV
t GLQX
t KHQZ
t ADKH
t DVKH
t EVKH
t KHAX
t KHDX
t KHEX
t KHKL
t KLKH
t ZZQZ
0 to 2.5 V
t ZZS
1.25 V
b l
t KHKH
MCM63F733A–10
Min
Output Timing Reference Level
Output Load
5.2
5.2
1.5
1.5
0.5
2 x
13
—
—
—
—
—
0
0
2
75 MHz
t KHKH
Max
. . . . . . . . . . . . . .
3.8
3.8
3.8
2 x
10
15
—
—
—
—
—
—
—
—
—
t KHKH
MCM63F733A–11
Min
1.5
1.5
0.5
2 x
15
—
—
—
—
—
6
6
0
0
2
See Figure 2 Unless Otherwise Noted
66 MHz
. . . . . . . . . . . . . . . . . . . . . . . . .
t KHKH
Max
3.8
3.8
3.8
2 x
11
15
—
—
—
—
—
—
—
—
—
MCM63F733A
U i
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
N
Notes
5, 6
5, 6
5, 6
5, 6
1.25 V
6
9