MCM63F733A Motorola, MCM63F733A Datasheet - Page 4

• Manufacturer Part Number: MCM63F733A
• Description: 128K x 32 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
• Manufacturer: Motorola

MCM63F733A
4
PIN DESCRIPTIONS
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
47, 48, 49, 50, 81, 82, 99, 100
4, 11, 20, 27, 54, 61, 70, 77
32, 33, 34, 35, 44, 45, 46,
14, 16, 38, 39, 42, 43, 66
55, 60, 67, 71, 76, 90
5, 10, 17, 21, 26, 40,
Pin Locations
(a) (b) (c) (d)
93, 94, 95, 96
15, 41, 65, 91
36, 37
85
84
83
86
89
31
98
97
92
88
87
64
SA1, SA0
Symbol
V DDQ
ADSC
ADSP
SGW
ADV
V DD
DQx
LBO
V SS
SBx
SE1
SE2
SE3
SW
NC
SA
ZZ
G
K
Supply
Supply
Supply
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
—
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
Asynchronous Output Enable Input.
Clock: This signal registers the address, data in, and all control signals
except G, LBO, and ZZ.
Linear Burst Order Input: This pin may be left floating; it will default as
interleaved.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Synchronous Byte Write Inputs: “x” refers to the byte being written
(byte a, b, c, d). SGW overrides SBx.
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
Synchronous Chip Enable: Active high for depth expansion.
Synchronous Chip Enable: Active low for depth expansion.
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
Sleep Mode: This active high asynchronous signal places the RAM into
the lowest power mode. The ZZ pin disables the RAMs internal clock
when placed in this mode. When ZZ is negated, the RAM remains in
low power mode until it is commanded to READ or WRITE. Data
integrity is maintained upon returning to normal operation.
Core Power Supply.
I/O Power Supply.
Ground.
No Connection: There is no connection to the chip.
Description
MOTOROLA FAST SRAM