MX23L6430 MACRONIX INTERNATIONAL, MX23L6430 Datasheet

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MX23L6430

Manufacturer Part Number
MX23L6430
Description
64M-Bit Synchronous Mask ROM
Manufacturer
MACRONIX INTERNATIONAL
Datasheet
www.DataSheet.co.kr
FEATURES
• Switchable organization : 4M x 16 ( word mode ) or 2M
• Power supply 3.0V ~ 3.6V
• TTL compatible with multiplexed address
• All inputs are sampled at rising edge of system clock
• Read performance :
GENERAL DESCRIPTION
The 64M synch. MROM is a synchronous high band-
width mask programmable ROM with MXIC's high per-
formance CMOS process technology and is organized
either as 4M x 16 bits or 2M x 32 bits depending on
polarity of WORD pin. Synchronous design allows pre-
cise cycle control , with the use of system clock, I/O
PIN CONFIGURATION
P/N:PM0575
x 32 ( double word mode )
- 4-1-1-1@33MHz(RAS Latency=1, CAS Latency=3 )
- 5-1-1-1@50MHz(RAS Latency=1, CAS Latency=4 )
- 7-1-1-1@66MHz(RAS Latency=2, CAS Latency=5 )
WORD
VCCQ
VCCQ
VCCQ
VCCQ
VSSQ
VSSQ
VSSQ
VSSQ
DQM
VCC
VCC
CAS
RAS
VCC
VCC
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
A12
A11
A10
MR
NC
CS
NC
NC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
MX23L6430
1
• MRS cycle with address key programs :
• DQM for data-out masking
• Package : 86 pin TSOP(II)
transaction are possible on every clock cycle. Range of
operating frequencies, programmable burst length and
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system application.
- 7-1-1-1@100MHz(RAS Latency=2, CAS Latency=5)
- Clock to valid output delay (tSAC) : 6ns(Max.)
- RAS Latency : 1 & 2
- CAS Latency : 2 ~ 8
- Burst Length : 8 double word
- Burst Type : Sequential or Interleaved
64M-Bit Synchronous Mask ROM
MX23L6430
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
Q31
VSSQ
Q15
Q30
VCCQ
Q14
Q29
VSSQ
Q13
Q28
VCCQ
Q12
NC
VSS
NC
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
NC
VSS
NC
Q27
VCCQ
Q11
Q26
VSSQ
Q10
Q25
VCCQ
Q9
Q24
VSSQ
Q8
VSS
PRELIMINARY
REV. 1.1, FEB. 09, 1999
INDEX
Datasheet pdf - http://www.DataSheet4U.net/

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MX23L6430 Summary of contents

Page 1

... MX23L6430 PRELIMINARY MX23L6430 64M-Bit Synchronous Mask ROM 86 VSS 85 Q31 84 VSSQ 83 Q15 82 Q30 81 VCCQ 80 Q14 79 Q29 78 VSSQ 77 Q13 76 Q28 75 VCCQ 74 Q12 VSS ...

Page 2

... Data output according to the rising edge of CLK Power and ground for the input buffers and the core logic immunity Double word mode / word mode, depending on polarity of WORD pin. Should be set before CAS enabling It works similar to OE during read operation 2 MX23L6430 Q0 : 64M bits : cell array Q31 CF2.0 ...

Page 3

... IOL -10uA 10uA VIH 2.0V VDD+0.3V VIL -0.3V 0.8V VOH 2.4V - VOL - 0.4V 3 INDEX MX23L6430 Conditions CKE=VIL, tCC=Min. CKE=0, tCC=Min. CS=VIH, tCC=Min., All outputs open (Note 1) tCC=Min., All outputs open 0<VIN<VDD+0.3V 0<VOUT<VDD+0.3V IOH=-2mA IOL=2mA REV. 1.1, FEB. 09, 1999 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 4

... VIH/VIL=2.4V/0.4V 1.4V tR/tF=1ns/1ns LVTTL 4 MX23L6430 up to 50MHz up to 33MHz MAX. MIN. MAX. 20ns - 30ns - - 6ns - 6ns 4ns - 4ns - 6.5ns - 11.5ns - 6.5ns - 11.5ns - 4ns - 4ns ...

Page 5

... DC Output Load Circuit CAPACITANCE PARAMETER Input Capacitance Output capacitance P/N:PM0575 3.3V 1200 ohms Output 50pF (2) AC Output Load Circuit SYMBOL MIN. MAX. UNIT Cin - 5 pF Cout - MX23L6430 1.4V 50 ohms Z0=50 ohms 50pF REV. 1.1, FEB. 09, 1999 INDEX Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 6

... DQM sampled at rising edge of a CLK makes a Hi-Z state or data output state, delayed by 2 CLK cycles. 4. NOP(No Operation) state on syn. MROM includes not only NOP but also precharge, refresh and write state on syn. DRAM . 5. Organization mode selection control is decided simutaneously with column access start, and according to the polarity of WORD pin. P/N:PM0575 MX23L6430 CKE CKE CS RAS CAS MR ...

Page 7

... MX23L6430 Burst Length Type A1 A0 Length sequential 0 0 reserved interleave reserved Interleave ® ® ...

Page 8

... the data written in the mode register. After mode register set command is completed, no new command can be issued for 3 clocks cycles. P/N:PM0575 MX23L6430 WORD MODE SELECTION CONTROL Mode selection control is decided simutaneously with column access according to WORD pin voltage level, high level for double word mode ( X32 ) and low level for word mode ( X16 ) ...

Page 9

... CAb RAb tOH tSAC Qa0 Qa1 Qa2 tRC Qa0 Qa1 Qa2 9 MX23L6430 Qa3 Qb0 Qb1 Qb2 Qb3 Qb0 Qa3 Qa4 Qa5 Qb1 Qb2 Qb3 REV. 1.1, FEB. 09, 1999 INDEX ...

Page 10

... CLK VIH CKE CS RAS CAS RAa Addr CAa BL=8 Data MR WORD P/N:PM0575 RAb Qa0 Qa1 Qa2 10 MX23L6430 CAb Qa5 Qa6 Qa3 Qa4 Qa7 Qb0 Qb1 REV. 1.1, FEB. 09, 1999 INDEX 18 Qb2 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 11

... Addr CAa Data BL=4 BL=8 Data MR WORD P/N:PM0575 CAb tCCD Qa0 Qa1 Qa2 Qa0 Qa1 Qa2 11 MX23L6430 CAc CAd Qc0 Qa3 Qb0 Qb1 Qb2 Qb3 Qc1 Qb2 Qa3 Qb0 Qb1 Qb3 Qc0 Qc1 REV. 1.1, FEB. 09, 1999 INDEX ...

Page 12

... Latency=2, CAS Latency=5, 100MHz CLK VIH CKE CS RAS CAS RAa Addr CAa BL=8 Data MR WORD P/N:PM0575 Qa0 Qa1 Qa2 12 MX23L6430 CAb Qa6 Qa3 Qa4 Qa5 Qa7 Qb0 Qb1 REV. 1.1, FEB. 09, 1999 INDEX 18 Qb2 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 13

... CAS RAa Addr CAa Data BL=4 BL=8 Data MR WORD P/N:PM0575 CAb Qa0 Qa1 Qa2 Qa0 Qa1 Qa2 13 MX23L6430 CAc CAd RAd tCR Qc0 Qa3 Qb0 Qb1 Qb2 Qb3 Qc1 Qb2 Qa3 Qb0 Qb1 Qb3 Qc0 Qc1 REV. 1.1, FEB. 09, 1999 ...

Page 14

... READ CYCLE 6: Mode Register Set CLK VIH CKE CS RAS CAS Code Addr Data MR MRS P/N:PM0575 RAa Hi-Z Row Active 14 MX23L6430 REV. 1.1, FEB. 09, 1999 INDEX 18 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 15

... CLK CKE Internal CLK CS RAS CAS RAa Addr CAa BL=8 Data MR WORD P/N:PM0575 Qa0 Qa1 Qa2 Clock Clock suspend suspend 15 MX23L6430 Qa6 Qa3 Qa4 Qa5 Qa7 exit REV. 1.1, FEB. 09, 1999 INDEX 18 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 16

... Latency=2, CAS Latency=5, 100MHz CLK CKE Internal CLK CS RAS CAS Addr Data Qa6 Qa7 MR WORD P/N:PM0575 power power down down exit 16 MX23L6430 RAa CAa row active REV. 1.1, FEB. 09, 1999 INDEX 18 Qa0 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 17

... Case 1) during burst read operation 0 1 Command RD data (CAS latency=2) data (CAS latency=3) data (CAS latency=4) data (CAS latency=5) Col Active P/N:PM0575 PRE STOP Qa1 Qa0 Qa1 Qa0 Qa1 Qa0 Qa0 17 INDEX MX23L6430 Qa1 REV. 1.1, FEB. 09, 1999 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 18

... Case 2) between read command and data out Command data (CAS latency=2) data (CAS latency=3) data (CAS latency=4) data (CAS latency=5) Col Active P/N:PM0575 PRE STOP Qa0 Qa0 Qa0 Qa0 18 INDEX MX23L6430 REV. 1.1, FEB. 09, 1999 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 19

... CS RAS CAS RAa CAa Addr Data DQM MR WORD Row Active Burst Read P/N:PM0575 tCL tCH CAb RAb Qa0 tSS 19 MX23L6430 Qb0 Qa3 Qb1 Qb2 Qb3 REV. 1.1, FEB. 09, 1999 INDEX 18 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 20

... REVISION HISTORY REVISION DESCRIPTION 1.1 To Add 100MHz Speed Grade P/N:PM0575 MX23L6430 PAGE P1,4 20 INDEX DATE Feb/09/1999 REV. 1.1, FEB. 09, 1999 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 21

... TEL:+886-3-509-3300 FAX:+886-3-509-2200 ACRONIX MERICA, NC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MX23L6430 C L O., TD. MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 21 INDEX Datasheet pdf - http://www.DataSheet4U.net/ ...

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