MX23L6430 MACRONIX INTERNATIONAL, MX23L6430 Datasheet - Page 4

• Manufacturer Part Number: MX23L6430
• Description: 64M-Bit Synchronous Mask ROM
• Manufacturer: MACRONIX INTERNATIONAL

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AC CHARACTERISTIC (Ta=0° C~70° C, VCC=3.3V±0.3V)
Note 1: (RAS latency+CAS latency)@33MHz, (RAS latency+CAS latency-1)@50MHz, 66MHz,100MHz
Note 2: Equal to (CAS latency)@33MHz, (CAS latency-1)@50MHz, 66MHz, 100MHz
AC TEST CONDITION
*Note: If CLK transition time is longer than 1ns, timing
P/N:PM0575
Item
CLK Cycle Time
CLK to Valid Output Delay
Data Output Hold Time
CLK High Pulse Width
CLK Low Pulse Width
Input Setup Time
Input Hold Time
CLK to Output in Low-Z
CLK to Output in High-Z
Power Down Exit Setup Time tPDE
Row Active to Row Active
CAS Enable to Row Active
Valid CAS Enable to
Valid CAS Enable
Input Pulse levels
Input and Output Timing Levels
Input Rise and Fall Times
Output Load
parameters should be compensated. Add
(tR+tF)/2-1ns for transition time longer than 1ns.
Transitions time is measured between VIL(Max.)
and VIH(Min.)
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
Symbol up to 100MHz
tRC
tCR
tCCD
VIH/VIL=2.4V/0.4V
1.4V
tR/tF=1ns/1ns
LVTTL
tSS+tCC-
MIN.
10ns
-
4ns
3ns
3ns
4ns
2ns
0ns
-
6 cycles -
4 cycles -
4 cycles -
-
MAX. MIN.
-
6ns
-
-
-
-
-
6ns
4
15ns
-
4ns
4ns
4ns
4ns
2ns
0ns
-
tSS+tCC -
up to 66MHz
6 cycles -
4 cycles -
4 cycles -
MAX. MIN.
-
6ns
-
-
-
-
-
-
10ns -
20ns
-
4ns
6.5ns
6.5ns
4ns
2ns
0ns
tSS+tCC -
up to 50MHz
4 cycles -
3 cycles -
3 cycles -
MX23L6430
MAX. MIN.
-
6ns
-
-
-
-
-
-
15ns -
up to 33MHz
30ns
-
4ns
11.5ns
11.5ns
4ns
2ns
0ns
tSS+tCC -
4 cycles - (Note 1)
3 cycles - (Note 2)
3 cycles - (Note 2)
REV. 1.1, FEB. 09, 1999
MAX.
-
6ns
-
-
-
-
-
-
25ns
INDEX
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