MX23L6430 MACRONIX INTERNATIONAL, MX23L6430 Datasheet - Page 8

• Manufacturer Part Number: MX23L6430
• Description: 64M-Bit Synchronous Mask ROM
• Manufacturer: MACRONIX INTERNATIONAL

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DEVICE OPERATION
CLOCK (CLK)
The clock input (CLK) is used as the reference for
SMROM synchronous operation with square wave sig-
nal applied externally at cycle time tCC. All operations
are synchronized to the rising edge of the clock. The
clock transition must be monotonic between VIL and VIH
. During operation with CKE high, all inputs are assumed
to be in valid state for the duration of set-up and hold
time around positive edge of the clock.
CLOCK ENABLE (CKE)
The clock enable (CKE) gates the clock into the SMROM
and is asserted high during all cycles, except power
down, and clock suspend mode. CKE should be en-
abled at least one cycle prior to new command. Disable
input buffers for power down in standby. CKE should be
enabled tPDE prior to valid command. In power down or
clock suspend mode, if the CKE goes low synchronously
with clock ( set-up and hold time ), the internal clock is
suspended from the next clock eycle. The power down
exit is synchronous as the internal clock is suspended.
When CKE goes high at least “tPDE” before the posi-
tive edge of CLK, the chip becomes active from the same
clock edge to accept all the input commands.
NOP (No Operation)
When RAS, CAS and MR are high, the SMROM per-
forms no operation (NOP) and does not initiate any new
command. The device deselect is also a NOP and is
entered by asserting CS high. CS high disables the com-
mand decoder so that RAS, CAS, MR and all the ad-
dress inputs are ignored. NOP of SMROM inclides
precharge, refresh, and write state of SDRAM. In addi-
tion, when mode register set command is entered in the
middle of normal operation, for SMROM, it's an illegal
state .
MODE REGISTER SET (MR)
The mode register stores the data for controlling the vari-
ous operating modes of SMROM including RAS latency,
CAS latency, burst type and burst length. The default
value of the mode register can be defined by ROM code
option. The mode register is programmed by asserting
low on CS, RAS, CAS, and MR and the states of the
address pins A0 ~ A6 is the data written in the mode
register. After mode register set command is completed,
no new command can be issued for 3 clocks cycles.
P/N:PM0575
8
WORD MODE SELECTION CONTROL
Mode selection control is decided simutaneously with
column access according to WORD pin voltage level,
high level for double word mode ( X32 ) and low level for
word mode ( X16 ).
ADDRESS DECODING
The address pins are latched by externally applying two
commands. The first command, RAS asserted low,
latches the row address into the device. A second com-
mand, CAS asserted low, subsequently latches the col-
umn address .
DQM OPERATION
The DQM is used to mask output operation and works
similar to OE. The DQM masking occurs two cycles later
in the read cycle, and operates synchronously with clock.
LATENCY
There is latency between when a read command is given
and when data is available on the I/O buffers. The RAS
to CAS delay is defined as the RAS latency, and the
CAS to data delay is the CAS latency.
BURST READ
The burst read command is used to access burst of data
on consecutive clock cycles from an active row state.
The burst read command is issued by asserting low on
CS and CAS with RAS and MR high on the positive edge
of the clock, after RAS latency number of clock cycles
from row active command .The first output appears in
CAS latency number of clock cycles after the issue of
burst read command. The output goes into high-imped-
ance at the end of the burst, unless a new burst read is
initiated to keep data gapless. The burst stop command
is valid during burst data out or between read command
and data out. The data bus go to Hi-Z after the CAS
latency from the burst stop command is satisfied. The
burst stop command is asserted CS, MR low and CAS,
RAS high or the same state as pre-charge on SDRAM.
The interval between read command ( column address
presented ) and burst stop command is one cycle mini-
mum .The interval between the burst stop command and
the next row active command is also one cycle mini-
mum.
MX23L6430
REV. 1.1, FEB. 09, 1999
INDEX
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