MX25U8035 Macronix International, MX25U8035 Datasheet - Page 14

• Manufacturer Part Number: MX25U8035
• Description: (MX25U4035 / MX25U8035) 4M-BIT [x 1/x 2/x 4] 1.8V CMOS SERIAL FLASH
• Manufacturer: Macronix International

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DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS,
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
Figure 1. Serial Modes Supported
P/N: PM1394
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
(Serial mode 0)
(Serial mode 3)
eration.
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
next CS# rising edge.
The difference of Serial mode 0 and mode 3 is shown as Figure 1. "Serial Modes Supported".
REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data
being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE,
CE, PP, 4PP, CP, RDP, DP, ENSO, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.
ed and not affect the current operation of Write Status Register, Program, Erase.
CPOL
0
1
CPHA
0
1
SI
SO
SCLK
SCLK
MSB
shift in
14
shift out
MX25U4035
MX25U8035
MSB
REV. 1.0, MAR. 09, 2009
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