MX26LV800T Macronix, MX26LV800T Datasheet
MX26LV800T
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MX26LV800T Summary of contents
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... Erase verify capability. - Automatically program and verify data at specified address GENERAL DESCRIPTION The MX26LV800T 8-mega bit high speed Flash memory organized as 1M bytes of 8 bits or 512K words of 16 bits. MXIC's high speed Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory ...
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... CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down A13 A12 A14 A10 4 WE# RESET RY/BY# NC A18 2 A7 A17 P/N:PM1007 MX26LV800T/B PIN DESCRIPTION SYMBOL PIN NAME A0~A18 48 A16 47 BYTE# Q0~Q14 46 GND 45 Q15/A-1 Q15/A Q14 CE Q13 WE Q12 BYTE# ...
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... BLOCK STRUCTURE TABLE 1: MX26LV800T SECTOR ARCHITECTURE Sector Sector Size Byte Mode Word Mode SA0 64Kbytes 32Kwords SA1 64Kbytes 32Kwords SA2 64Kbytes 32Kwords SA3 64Kbytes 32Kwords SA4 64Kbytes 32Kwords SA5 64Kbytes 32Kwords SA6 64Kbytes 32Kwords SA7 64Kbytes 32Kwords SA8 64Kbytes 32Kwords SA9 ...
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... SA15 64Kbytes 32Kwords SA16 64Kbytes 32Kwords SA17 64Kbytes 32Kwords SA18 64Kbytes 32Kwords Note: Byte mode:address range A18:A-1, word mode:address range A18:A0. P/N:PM1007 MX26LV800T/B Address range Byte Mode (x8) Word Mode (x16) 00000h-03FFFh 00000h-01FFFh 04000h-05FFFh 02000h-02FFFh 06000h-07FFFh 03000h-03FFFh 08000h-0FFFFh 04000h-07FFFh 10000h-1FFFFh 08000h-0FFFFh 20000h-2FFFFh ...
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... BLOCK DIAGRAM CE# CONTROL OE# INPUT WE# LOGIC RESET# ADDRESS LATCH A0-A18 AND BUFFER Q0-Q15/A-1 P/N:PM1007 MX26LV800T/B PROGRAM/ERASE HIGH VOLTAGE MX26LV800T/B FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 5 WRITE STATE MACHINE (WSM) STATE REGISTER COMMAND DATA DECODER ...
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... Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX26LV800T/B is less than 35 seconds. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the ...
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... TABLE 3. MX26LV800T/B AUTO SELECT MODE OPERATION Description Mode CE# OE# WE# Manufacturer Code Read Device ID Word Silicon (Top Boot Block) Byte ID Device ID Word (Bottom Boot Block) Byte NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High P/N:PM1007 MX26LV800T/B A18 A11 A12 A10 ...
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... TABLE 4. MX26LV800T/B COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon ID Word 4 555H AAH 2AAH Byte 4 AAAH AAH 555H Program Word 4 555H AAH 2AAH Byte 4 AAAH AAH 555H Chip Erase Word 6 555H AAH 2AAH ...
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... Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences. TABLE 5. MX26LV800T/B BUS OPERATION DESCRIPTION CE# OE# WE# RESET# A18 A10 ...
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... Sequence section for more information. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The "AC P/N:PM1007 MX26LV800T/B Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODE When using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at Vcc ± ...
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... ID command sequence into the command register. Fol- lowing the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of DAH/22DAH for MX26LV800T, 5BH/225BH for MX26LV800B. P/N:PM1007 MX26LV800T/B SET-UP AUTOMATIC CHIP/SECTOR ERASE COMMANDS Chip erase is a six-bus cycle operation ...
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... TABLE 6. SILICON ID CODE Pins A0 Manufacture code Word VIL Byte VIL Device code Word VIH for MX26LV800T Byte VIH Device code Word VIH for MX26LV800B Byte VIH READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to re- trieve data ...
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... The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, P/N:PM1007 MX26LV800T/B followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings ...
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... Table 7 shows the outputs for RY/BY# during write op- eration. P/N:PM1007 MX26LV800T/B Q6:Toggle BIT I Toggle Bit indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the ...
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... If this time-out condition occurs during the chip erase P/N:PM1007 MX26LV800T/B operation, it specifies that the entire chip is bad or com- bination of sectors are bad. If this time-out condition occurs during the word/byte programming operation, it specifies that the entire sec- ...
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... Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5:Exceeded Timing Limits " for more information. P/N:PM1007 MX26LV800T (Note1) ...
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... In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. POWER-UP SEQUENCE The MX26LV800T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. P/N:PM1007 MX26LV800T/B OPERATING RATINGS Commercial (C) Devices +150 C ...
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... If VIH is over the specified maximum value, read operation cannot be guaranteed. 3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns. P/N:PM1007 MX26LV800T/B MIN. TYP MAX VCC = 3.0V~3.6V MX26LV800T/B MIN. TYP MAX 200 ...
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... Input rise and fall times is equal to or less than 5ns. • Output load: 1 TTL gate + 100pF (Including scope and jig), for 26LV800T/B-70. 1 TTL gate + 30pF (Including scope and jig) for 26LV800T/B-55. • Reference levels for measuring timing: 1.5V. P/N:PM1007 MX26LV800T VCC = 3.0V~3.6V 26LV800T/B-55 26LV800T/B-70 MIN ...
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... SWITCHING TEST WAVEFORMS 3. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. P/N:PM1007 MX26LV800T/B CL 6.2K ohm CL= 100pF Including jig capacitance for MX26LV800T/B-70 (30pF for MX26LV800T/B-55) TEST POINTS INPUT 21 2.7K ohm +3.3V DIODES=IN3064 OR EQUIVALENT OUTPUT REV ...
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... FIGURE 1. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL VIH RESET# VIL P/N:PM1007 MX26LV800T/B tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 22 tDF HIGH Z REV. 1.2, JUL. 08, 2004 ...
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... VCC Setup Time (Note 1) tRB Recovery Time from RY/BY# tBUSY Program/Erase Valid to RY/BY# Delay tBAL Sector Address Load Time NOTES: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM1007 MX26LV800T VCC = 3.0V~3.6V 26LV800T/B-55 MIN. MAX ...
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... WE# Hold Time tCP CE# Pulse Width tCPH CE# Pulse Width High tWHWH1 Programming Operation(note2) tWHWH2 Sector Erase Operation (note2) NOTE: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM1007 MX26LV800T VCC = 3.0V~3.6V 26LV800T/B-55 MIN. MAX ...
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... FIGURE 2. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1007 MX26LV800T/B ADD Valid tAH tWP tCWC tCH tDS tDH DIN 25 tWPH REV. 1.2, JUL. 08, 2004 ...
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... VCC NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address P/N:PM1007 MX26LV800T/B ing after automatic programming starts. Device outputs DATA# during programming and DATA# after program- ming on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) ...
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... FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1007 MX26LV800T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Word Ok ? YES No Last Address ? YES Auto Program Completed 27 REV ...
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... Data tRH RESET# RY/BY# NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence. P/N:PM1007 MX26LV800T/B PA for program SA for sector erase 555 for chip erase Data# Polling tAS tAH tWHWH1 or 2 tCPH ...
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... VCC NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1007 MX26LV800T/B matic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) Read Status Data ...
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... FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1007 MX26LV800T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data Pall from System ...
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... NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1007 MX26LV800T/B ing after automatic erase starts. Device outputs 0 dur- ing erasure and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle bit, DATA# polling, timing waveform) ...
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... FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1007 MX26LV800T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address NO Last Sector ...
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... WRITE OPERATION STATUS FIGURE 10. DATA# POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1007 MX26LV800T/B Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? Yes Read Q7~Q0 Add.=VA Yes Q7 = Data ? (2) No FAIL 33 Pass REV. 1.2, JUL. 08, 2004 ...
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... FIGURE 11. TOGGLE BIT ALGORITHM NO Program/Erase Operation Not Complete,Write Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1007 MX26LV800T/B Start Read Q7-Q0 Read Q7-Q0 (Note 1) NO Toggle Bit Q6 = Toggle ? YES Q5= 1? ...
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... WE# Q7 Q0-Q6 tBUSY RY/BY# NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle. 2. CE# must be toggled when DATA# polling. P/N:PM1007 MX26LV800T/B VA tDF tOH Complement Complement True Status Data Status Data True ...
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... RY/BY# NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 2. CE# must be toggled when toggle bit toggling. P/N:PM1007 MX26LV800T/B VA tOE tDF tOH Valid Status Valid Status ...
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... RY/BY# Recovery Time (to CE#, OE# go low) Note: Not 100% tested FIGURE 14. RESET# TIMING WAVEFORM RY/BY# CE#, OE# RESET# Reset Timing NOT during Automatic Algorithms RY/BY# CE#, OE# RESET# Reset Timing during Automatic Algorithms P/N:PM1007 MX26LV800T/B Test Setup All Speed Options Unit MAX MAX tRH tRP tReady2 tReady1 tRP ...
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... BYTE# Switching Low to Output HIGH Z tFHQV BYTE# Switching High to Output Active FIGURE 15. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode) CE# OE# BYTE# Q0~Q14 Q15/A-1 P/N:PM1007 MX26LV800T/B Max Max Min tELFH DOUT (Q0-Q7) VA tFHQV 38 Speed Options Unit -55 ...
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... BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from word mode to byte mode) CE# OE# BYTE# Q0~Q14 Q15/A-1 FIGURE 17. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS CE# WE# BYTE# P/N:PM1007 MX26LV800T/B tELFH DOUT (Q0-Q14) DOUT VA (Q15) tFLQZ The falling edge of the last WE# signal tAS tAH 39 ...
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... VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A18 VIL CE# VIH VIL tCE VIH WE# VIL VIH OE# VIL VIH DATA VIL Q0-Q15 P/N:PM1007 MX26LV800T/B tACC tOE tOH DATA OUT C2H/00C2H 40 tDF tOH DATA OUT DAH/5BH (Byte) 22DAH/225BH (Word) REV. 1.2, JUL. 08, 2004 ...
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... Input Voltage with respect to GND on ACC, OE#, RESET#, A9 Input Voltage with respect to GND on all power pins, Address pins, CE# and WE# Input Voltage with respect to GND on all I/O pins Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N:PM1007 MX26LV800T/B LIMITS MIN. TYP. (2) MAX. (3) 2.4 ...
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... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX26LV800TTC-55 55 MX26LV800BTC-55 55 MX26LV800TTC-70 70 MX26LV800BTC-70 70 MX26LV800TXBC-55 55 MX26LV800BXBC-55 55 MX26LV800TXBC-70 70 MX26LV800BXBC-70 70 MX26LV800TXEC-55 55 MX26LV800BXEC-55 55 MX26LV800TXEC-70 70 MX26LV800BXEC-70 70 P/N:PM1007 MX26LV800T/B OPERATING STANDBY Current MAX. (mA) Current MAX. (uA) 30 100 30 100 30 100 30 100 30 100 30 100 30 100 30 100 30 100 30 100 30 100 30 100 42 PACKAGE ...
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... PACKAGE INFORMATION P/N:PM1007 MX26LV800T/B 43 REV. 1.2, JUL. 08, 2004 ...
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... CSP (for MX26LV800ATXBC/ATXBI/ABXBC/ABXBI) P/N:PM1007 MX26LV800T/B 44 REV. 1.2, JUL. 08, 2004 ...
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... CSP (for MX26LV800ATXEC/ATXEI/ABXEC/ABXEI) P/N:PM1007 MX26LV800T/B 45 REV. 1.2, JUL. 08, 2004 ...
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... Modified ILI data from 1(max.) to 1(typ.)/3(max.) 2. Removed "Advanced Information" title 1.1 1. Modified the erase/program cycling to 2K cycles 2. Removed data retention table 1.2 1. Modified the erase/program cycling to 2K cycles in General Description & Erase and Programming Performance notes P/N:PM1007 MX26LV800T/B Page P19 P1 P1,41 P41 P1,41 46 Date ...
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... MX26LV800T/B ...