MX26LV800T Macronix, MX26LV800T Datasheet - Page 29

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MX26LV800T

Manufacturer Part Number
MX26LV800T
Description
8M-Bit CMOS Single Voltage Flash Memory
Manufacturer
Macronix
Datasheet

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AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by DATA# polling and toggle bit checking after auto-
FIGURE 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM
P/N:PM1007
Address
RY/BY#
WE#
Data
VCC
OE#
CE#
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
tVCS
tCS
tGHWL
Erase Command Sequence(last two cycle)
tWC
2AAh
tWP
tDS tDH
55h
tCH
tWPH
tAS
555h
10h
tAH
29
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle
bit, DATA# polling, timing waveform)
tBUSY
Read Status Data
MX26LV800T/B
tWHWH2
VA
Progress Complete
In
VA
tRB
REV. 1.2, JUL. 08, 2004

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