MX26LV800T Macronix, MX26LV800T Datasheet - Page 14

• Manufacturer Part Number: MX26LV800T
• Description: 8M-Bit CMOS Single Voltage Flash Memory
• Manufacturer: Macronix

Q7: Data# Polling
The Data# Polling bit, Q7, indicates to the host system
whether an Automatic Algorithm is in progress or com-
pleted. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command se-
quence.
During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7. When the Automatic Program algorithm is com-
plete, the device outputs the datum programmed to Q7.
The system must provide the program address to read
valid status information on Q7.
During the Automatic Erase algorithm, Data# Polling pro-
duces a "0" on Q7. When the Automatic Erase algo-
rithm is complete, Data# Polling produces a "1" on Q7.
This is analogous to the complement/true datum out-put
described for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the device outputs the "complement,” or "0".” The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchronously with Q0-Q6 while Output En-
able (OE#) is asserted low.
RY/BY# : Ready/Busy
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY# status is valid
after the rising edge of the final WE# or CE#, whichever
happens first, in the command sequence. Since RY/BY#
is an open-drain output, several RY/BY# pins can be
tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. If the output is high (Ready), the device
is ready to read array data, or is in the standby mode.
Table 7 shows the outputs for RY/BY# during write op-
eration.
P/N:PM1007
14
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete. Toggle
Bit I may be read at any address, and is valid after the
rising edge of the final WE# or CE#, whichever happens
first, in the command sequence (prior to the program or
erase operation), and during the sector time-out.
During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle. The system may use either OE# or CE# to
control the read cycles. When the operation is complete,
Q6 stops toggling.
When the device is actively erasing (that is, the Auto-
matic Erase algorithm is in progress), Q6 toggling. How-
ever, the system must also use Q2 to determine which
sectors are erasing. Alternatively, the system can use
Q7.
Q6 stops toggling once the Automatic Program algo-
rithm is complete.
Table 7 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively erasing (that is,
the Automatic Erase algorithm is in process). Toggle Bit
II is valid after the rising edge of the final WE# or CE#,
whichever happens first, in the command sequence.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE# or CE# to control the read
cycles.) But Q2 cannot distinguish when the sector is
actively erasing. Q6, by comparison, indicates when
the device is actively erasing, but cannot distinguish
which sectors are selected for erasure. Thus, both sta-
tus bits are required for sectors and mode information.
Refer to Table 8 to compare outputs for Q2 and Q6.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
MX26LV800T/B
REV. 1.2, JUL. 08, 2004