isl22416 Intersil Corporation, isl22416 Datasheet - Page 10

• Manufacturer Part Number: isl22416
• Description: Low Noise, Low Power, Spi? Bus, 128 Taps
• Manufacturer: Intersil Corporation

The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR is recalled and
loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 7-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW)
is closest to its “Low” terminal (RL). When the WR register of
a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of
the WR increases from all zeroes (0) to all ones (127
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL22416 is being powered up, the WR is reset to
40h (64 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reload with the value stored in a non-
volatile Initial Value Register (IVR).
The WR and IVR can be read or written to directly using the
SPI serial interface as described in the following sections.
Memory Description
The ISL22416 contains one non-volatile 7-bit register, known
as the Initial Value Register (IVR), volatile 7-bit Wiper
Register (WR), and volatile 8-bit Access Control Register
(ACR). The memory map of ISL22416 is on Table 1. The
non-volatile register (IVR) at address 0, contain initial wiper
position and volatile registers (WR) contain current wiper
position.
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
ADDRESS
2
1
0
NON-VOLATILE
TABLE 1. MEMORY MAP
IVR
—
10
Reserved
VOLATILE
ACR
WR
ISL22416
The VOL bit (ACR<7>) determines whether the access is to
wiper registers WR or initial value registers IVR.
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR<6>) disables or enables Shutdown mode.
This bit is logically OR’d with SHDN pin. When this bit is 0, DCP
is in Shutdown mode. Default value of SHDN bit is 1.
The WIP bit (ACR<5>) is read only bit. It indicates that
non-volatile write operation is in progress. The WIP bit can
be read repeatedly after a non-volatile write to determine if
the write has been completed. It is impossible to write to the
WR or ACR while WIP bit is 1.
SPI Serial Interface
The ISL22416 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22416. SCK and CS lines are
controlled by the host or master. The ISL22416 operates
only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
The first byte sent to the ISL22416 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.
The next byte sent to the ISL22416 contains the instruction
and register pointer information. The four MSBs are the
instruction and two LSBs are register address (see Table 4).
There are only two valid instruction sets:
1011(binary) - is a Read operation
1100(binary) - is a Write operation
There are only two registers address possible for this DCP. If
the R1, R0 bits are zero, then the read or write is to either
(MSB)
NAME
BIT #
I3
BIT
0
7
TABLE 2. ACCESS CONTROL REGISTER (ACR)
TABLE 3. IDENTIFICATION BYTE FORMAT
TABLE 4. IDENTIFICATION BYTE FORMAT
I2
VOL
1
6
7
SHDN
I1
6
0
5
WIP
5
I0
1
4
4
0
0
3
0
3
0
0
2
0
2
0
R1
0
1
1
0
June 23, 2006
FN6227.0
(LSB)
R0
0
0
0
0