isl22416 Intersil Corporation, isl22416 Datasheet - Page 9

• Manufacturer Part Number: isl22416
• Description: Low Noise, Low Power, Spi? Bus, 128 Taps
• Manufacturer: Intersil Corporation

Typical Performance Curves
Pin Description
Potentiometer Pins
RH and RL
The high (RH) and low (RL) terminals of the ISL22416 are
equivalent to the fixed terminals of a mechanical
potentiometer. RH and RL are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WR set to 127 decimal, the wiper will be
closest to RH, and with the WR set to 0, the wiper is closest
to RL.
RW
RW is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
SHDN
The SHDN pin forces the resistor to end-to-end open circuit
condition on RH and shorts RW to RL. When SHDN is
returned to logic high, the previous latch settings put RW at
the same resistance setting prior to shutdown. This pin is
logically OR’d with SHDN bit in ACR register. SPI interface is
still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
9
RH
RW
RL
(Continued)
ISL22416
Bus Interface Pins
Serial Clock (SCK)
This is the serial clock input of the SPI serial interface.
Serial Data Output (SDO)
The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS input is low.
SDO requires an external pull-up resistor for proper
operation.
Serial Data Input (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
Chip Select (CS)
CS LOW enables the ISL22416, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22416 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
Principles of Operation
The ISL22416 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and the
SPI serial interface providing direct communication between
host and potentiometer and memory. The resistor array is
comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
FIGURE 14. LARGE SIGNAL SETTLING TIME
June 23, 2006
FN6227.0