mpc9894 ETC-unknow, mpc9894 Datasheet - Page 16

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Test Access Port (TAP) and Boundary Scan Architecture
implementation in the MPC9894. Special private instructions
are provided to assist in production test control. These
instructions combined with control of the test mode inputs
Instruction Register
Instructions
implementation and their instruction codes. Public
Boundary-Scan Register
Device Identification Register (0x0281D01D)
MPC9894
16
Table 29. TAP Interface Signals
Table 30. Instruction Register
Table 31. TAP Controller Public Instructions
Table 32. Device Identification Register
Position
Value
This section describes the IEEE Std. 1149.1 compliant
Table 31
A full description of the boundary scan register may be found in the BSDL file.
Field
Bit
Signal Name
TRST_B
TMS
TDO
Instruction
TCK
TDI
BYPASS
SAMPLE
EXTEST
IDCODE
CLAMP
HIGHZ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
lists the public instructions provided in the
0
Capture-IR Value
Version
0
Bit Position
Field
0
0
0
Test Mode Select
Test Reset Bar
Test Data Out
0
Description
Test Data In
Test Clock
1
Code
11111
01100
00000
01001
00001
00010
0
1
0
0
Part Number
IEEE STD.1149.1(JTAG)
4
0
0
0
Asynchronous test controller reset.
Serial test instruction/data output.
0
Serial test instruction/data input.
0
TAP mode control input.
1
and the use of shared inputs and outputs provide for full
production test mode access and control.
Test Access Port Interface Signals
descriptions.
instructions are accessible by the customer for board test and
may also be used for production chip test.
Test logic clock.
3
0
Table 29
Function
1
Enabled Serial Test Data Path
1
0
Boundary Scan Register
Boundary Scan Register
lists the TAP interface signals and their
1
Bypass Register
Bypass Register
Bypass Register
IR
ID Register
2
0
0
0
0
Advanced Clock Drivers Devices
8
0
Manufacturer ID
7
0
Direction
Output
1
0
Freescale Semiconductor
Input
Input
Input
Input
6
0
5
0
4
1
Active State
3
1
2
1
0
1
—
—
—
—
—
1
0
0
1