mpc9894 ETC-unknow, mpc9894 Datasheet - Page 7

• Manufacturer Part Number: mpc9894
• Description: Quad Input Redundant Idcs Clock Generator
• Manufacturer: ETC-unknow

Advanced Clock Drivers Devices
Freescale Semiconductor
clocks is the current reference clock. In the automatic mode
and In the case of the reference clock failure, the SEL_STAT
its lowest frequency. This condition will be indicated by the
LOCK pin being de-asserted. The MPC9894 will remain in
this state until an input clock is restored and the device is
reset via the MR pin.
Clock Failure Detection
an input clock amplitude check combined with an activity
detector. The following conditions will trigger a failed clock
status (CLK_STATn = 0) on any qualified clock
(CLK_VALIDn = 1). These conditions are:
1.
2.
3.
4.
5.
phase-frequency detector after the input divider (P). This is
Table 4. Input Clock Qualifier and Status Flag
Table 5. Input Clock Status CLK_STAT[3:0]
Table 6. Clock Input Qualifier CLK_VALID[3:0]
Table 7. SEL_STAT[1:0]
1. The input qualifier logic can be enabled or disabled by setting the QUAL_EN bit in register 3.
The SEL_STAT[1:0] pins indicate which of the four input
If all four clock inputs are not qualified the VCO will slew to
The MPC9894 clock failure detection is performed using
In addition, the currently selected clock is checked by a
Input Clock
Either or both CLKx, CLKx are disconnected from the
input clock source and open.
CLKx and CLKx are shorted together
Either or both CLKx or CLKx are shorted to GND
Both CLKx and CLKx are shorted to a power supply
Amplitude of CLKx or CLKx is less than V
AC specification,
CLK0
CLK1
CLK2
CLK3
Associated Input Qualifier
Table
SEL_STAT[1:0]
CLK_VALID[]
CLK_STAT[]
CLK_VALID0
CLK_VALID1
CLK_VALID2
CLK_VALID3
39)
00
01
10
11
0
1
0
1
(1)
PP, OK
(refer to
CLK_STAT0
CLK_STAT1
CLK_STAT2
CLK_STAT3
Pin
Not qualified and will not be selected
Qualified
flag will indicate a reference clock different from the original
primary clock selected by IDCS_MODE[2:0]. The CLK_STAT
outputs are mirrored in register 5, bits 1:0 for I
triggered by a phase step of mae
issue a failed clock status (CLK_STATn = 0) within 'P' clock
cycles.
frequency or the reference frequency being out of the
specified input frequency range. This includes errors such as
reference frequency drift due to crystal aging etc.
Clearing of IDCS Alarm Flags
remain set until manually cleared (sticky). Clearing can be
done by either of two methods. All status flags can be cleared
by the package pin, CLK_ALARM_RST. Or individual status
flags can be cleared via register bits, ALARM_RST[3:0]. The
CLK_ALARM_RST pin is activated by a negative edge on the
pin. This clears all CLK_STAT[3:0] flags and returns the IDCS
to the primary clock source. The SEL_STAT[1:0]-selected
clock indicator now reflects the IDCS_MODE[2:0] setting.
CLK_STAT[3:0] bits are cleared by writing a logic 0 to the
individual bit in this register. It is important to note that this
action does not return the IDCS to the primary clock.
The IDCS does not detect changes of the reference
The input clock status flags are set by a clock failure and
By using ALARM_RST[3:0] (register 2) individual
Associated Input Clock Status Flag
Associated Input Clock
Clock input signal valid
Selected clock input
Clock input failure
Description
CLK0
CLK1
CLK2
CLK3
Device register 5, bit 3
Device register 5, bit 4
Device register 5, bit 5
Device register 5, bit 6
Register location
(∅)
. This phase detector will
2
C bus access.
MPC9894
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