adc10dv200cisq National Semiconductor Corporation, adc10dv200cisq Datasheet

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adc10dv200cisq

Manufacturer Part Number
adc10dv200cisq
Description
Adc10dv200 Dual 10-bit, 200 Msps Low-power A/d Converter With Parallel Outputs
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2009 National Semiconductor Corporation
Dual 10-bit, 200 MSPS Low-Power A/D Converter with
Parallel LVDS/CMOS Outputs
General Description
The ADC10DV200 is a monolithic analog-to-digital converter
capable of converting two analog input signals into 10-bit dig-
ital words at rates up to 200 Mega Samples Per Second
(MSPS). The digital output mode is selectable and can be ei-
ther differential LVDS or CMOS signals. This converter uses
a differential, pipelined architecture with digital error correc-
tion and an on-chip sample-and-hold circuit to minimize die
size and power consumption while providing excellent dy-
namic performance. A unique sample-and-hold stage yields
a full-power bandwidth of 900MHz. Fabricated in core CMOS
process, the ADC10DV200 may be operated from a single
1.8V power supply. The ADC10DV200 achieves approxi-
mately 9.6 effective bits at Nyquist and consumes just 280mW
at 170MSPS in CMOS mode and 450mW at 200MSPS in
LVDS mode. The power consumption can be scaled down
further by reducing sampling rates.
Applications
Block Diagram
Communications
Medical Imaging
Portable Instrumentation
Digital Video
300820
ADC10DV200
Features
Key Specifications
Single 1.8V power supply operation.
Power scaling with clock frequency.
Internal sample-and-hold.
Internal or external reference.
Power down mode.
Offset binary or 2's complement output data format.
LVDS or CMOS output signals.
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
Clock Duty Cycle Stabilizer.
IF Sampling Bandwidth > 900MHz.
Resolution
Conversion Rate
ENOB
SNR
SINAD
SFDR
LVDS Power
CMOS Power
Operating Temp. Range
59.9 dBFS (typ) @Fin=70MHz
59.9 dBFS (typ) @Fin=70MHz
450mW (typ) @Fs=200MSPS
280mW (typ) @Fs=170MSPS
82 dBFS (typ) @Fin=70MHz
9.6 bits (typ) @Fin=70MHz
30082002
February 5, 2009
−40°C to +85°C.
www.national.com
200 MSPS
10 Bits

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adc10dv200cisq Summary of contents

Page 1

... Applications ■ Communications ■ Medical Imaging ■ Portable Instrumentation ■ Digital Video Block Diagram © 2009 National Semiconductor Corporation ADC10DV200 Features ■ Single 1.8V power supply operation. ■ Power scaling with clock frequency. ■ Internal sample-and-hold. ■ Internal or external reference. ...

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... Connection Diagram Ordering Information Industrial (−40°C ADC10DV200CISQE www.national.com ≤ ≤ T +85°C) A ADC10DV200CISQ 250 pc. Tape and Reel ADC10DV200EB 2 30082001 Package 60 Pin LLP 60 Pin LLP, Evaluation Board ...

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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I ...

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Pin No. Symbol DIGITAL I/O 57 CLK + 56 CLK - 36 PD_A 53 PD_B 23 OUTSEL LVDS Output Mode 24, 25 D0+,D0- 26, 27 D1+, D1- 28, 29 D2+, D2- 32, 33 D3+, D3- 34, 35 D4+, D4- 39, ...

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Pin No. Symbol CMOS Output Mode 24-29, DA0-DA9 32-35 39-44, DB0-DB9 47-50 37 DRDYA 38 DRDYB 51 ORA 52 ORB ANALOG POWER 8, 16, 18, 59 12, 15, AGND 22, 55, 58, EP DIGITAL POWER ...

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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage on Any Pin (Not to exceed 2.2V) Input ...

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Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for T ≤ ≤ apply for T ...

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Input/Output Logic Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for T ≤ ≤ All other ...

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Symbol Parameter CMOS OUTPUT MODE (Notes 12, 16) Maximum Clock Frequency Minimum Clock Frequency t Clock High Time Conversion Latency CONV t Output Delay of CLK to DATA OD t Data Output Setup Time(Note 16) SU ...

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Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...

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Timing Diagrams FIGURE 1. LVDS Output Timing FIGURE 2. CMOS Output Timing 11 30082009 30082016 www.national.com ...

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Transfer Characteristic www.national.com FIGURE 3. Transfer Characteristic 12 30082010 ...

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Typical Performance Characteristics DNL, INL specifications apply: AGND = DRGND = 0V 25° DNL Unless otherwise specified, the following = +1.8V 200 MHz, 50% ...

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Typical Performance Characteristics AGND = DRGND = 0V MHz 25°C. A SNR, SINAD, SFDR vs. V SNR, SINAD, SFDR vs. Temperature SNR, SINAD, SFDR vs. Clock Duty Cycle, f www.national.com ...

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SNR, SINAD, SFDR vs. Ext. Reference Voltage SNR, SINAD, SFDR vs. Clock Frequency SNR, SINAD, SFDR vs. Ext. V Distortion vs. Ext. Reference Voltage 30082057 Distortion vs. Clock Frequency 30082059 Distortion vs. Ext 30082061 15 30082058 30082060 CM ...

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Spectral Response @ 10 MHz Input Spectral Response @ 170 MHz Input Total Power vs. Clock Frequency, f www.national.com Spectral Response @ 70 MHz Input 30082063 IMD, f 30082065 = 10 MHz IN 30082067 16 30082064 MHz, ...

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Functional Description Operating on a single +1.8V supply, the ADC10DV200 digi- tizes two differential analog input signals to 10 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. The user ...

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− REF CM V − REF − REF CM V ...

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A 0.1 µF capacitor should be placed between V and V as close to the pins as pos sible. This configuration is shown ...

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www.national.com 20 ...

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POWER SUPPLY CONSIDERATIONS The power supply pins should be bypassed with a 0.1 µF ca- pacitor and with a 100 pF ceramic chip capacitor close to each power pin. Leadless chip capacitors are preferred because they have low series ...

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... Physical Dimensions TOP View...............................SIDE View...............................BOTTOM View www.national.com inches (millimeters) unless otherwise noted 60-Lead LLP Package Ordering Numbers: ADC10DV200CISQ NS Package Number SQA60A 22 ...

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Notes 23 www.national.com ...

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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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