adc10dv200cisq National Semiconductor Corporation, adc10dv200cisq Datasheet - Page 4

• Manufacturer Part Number: adc10dv200cisq
• Description: Adc10dv200 Dual 10-bit, 200 Msps Low-power A/d Converter With Parallel Outputs
• Manufacturer: National Semiconductor Corporation

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DIGITAL I/O
LVDS Output Mode
Pin No.
24, 25
26, 27
28, 29
32, 33
34, 35
39, 40
41, 42
43, 44
47, 48
49, 50
57
56
36
53
23
37
38
51
52
OUTSEL
D1+, D1-
D2+, D2-
D3+, D3-
D4+, D4-
D5+, D5-
D6+, D6-
D7+, D7-
D8+, D8-
D9+, D9-
D0+,D0-
Symbol
DRDY+
DRDY-
CLK +
CLK -
PD_A
PD_B
OR+
OR-
Equivalent Circuit
4
Clock input pins signal. The analog inputs are sampled on the
rising edge of this signal. The clock can be configured for
single-ended mode by shorting the CLK- pin to AGND. When
in differential mode, the common mode voltage for the clock
is internally set to 1.2V.
Two-state input controlling Power Down.
PD = V
reduced.
PD = AGND, Normal operation.
Two-state input controlling Output Mode.
OUTSEL = V
OUTSEL = AGND, CMOS Output Mode.
LVDS Output pairs for bits 0 through 9. A-channel and B-
channel digital LVDS outputs are interleaved. A channel is
ready at rising edge of DRDY and B channel is ready at the
falling edge of DRDY.
Data Ready Strobe. This signal is a LVDS DDR clock used to
capture the output data. A-channel data is valid on the rising
edge of this signal and B-channel data is valid on the falling
edge.
ADC over-range Signal. This signals timing is formatted
similarly to the data output signals. A channel is valid on DRDY
rising and B channel is valid on DRDY falling. This signal will
go high when the respective channel exceeds the allowable
range of the ADC. Nominally this signal will be low.
A
, Power Down is enabled and power dissipation is
D
, LVDS Output Mode.
Description