adc10dv200cisq National Semiconductor Corporation, adc10dv200cisq Datasheet - Page 9

• Manufacturer Part Number: adc10dv200cisq
• Description: Adc10dv200 Dual 10-bit, 200 Msps Low-power A/d Converter With Parallel Outputs
• Manufacturer: National Semiconductor Corporation

CMOS OUTPUT MODE (Notes 12, 16)
t
t
t
t
t
t
t
t
Symbol
CH
CL
CONV
OD
SU
H
AD
AJ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: Units of dBFS indicates the value that would be attained with a full-scale input signal.
Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
Note 4: When the input voltage at any pin exceeds the power supplies (that is, V
±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.
Note 5: The maximum allowable power dissipation is dictated by T
can be calculated using the formula P
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such
conditions should always be avoided.
Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0Ω resistor. Charged device model
simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 8: The inputs are protected as shown below. Input voltage magnitudes above V
(Note 4). However, errors in the A/D conversion can occur if the input goes above V
Note 9: With a full scale differential input of 1.5V
Note 10: Typical figures are at T
guaranteed.
Note 11: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
Note 12: CMOS Specifications are for F
Note 13: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dBFS lower.
Note 14: SFDR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 2dBFS lower.
Note 15: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.1dBFS lower.
Note 16: This parameter is guaranteed by design and/or characterization and is not tested in production.
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Conversion Latency
Output Delay of CLK to DATA
Data Output Setup Time(Note 16)
Data Output Hold Time(Note 16)
Aperture Delay
Aperture Jitter
Parameter
A
= 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not
D,max
CLK
= (T
= 170 MHz.
J,max
P-P
, the 10-bit LSB is 1.465mV.
- T
A
)/θ
JA
. The values for maximum power dissipation listed above will be reached only when the device is
DCS On
DCS Off
DCS On
DCS Off
DCS On
DCS Off
Relative to falling edge of CLK
Relative to DRDY
Relative to DRDY
J,max
, the junction-to-ambient thermal resistance, (θ
9
Conditions
IN
< AGND, or V
A
A
or below AGND.
or below GND will not damage this device, provided current is limited per
30082011
IN
> V
A
), the current at that pin should be limited to ±5 mA. The
(Note 10)
JA
Typical
), and the ambient temperature, (T
4.5
2.5
3.4
0.7
0.3
Limits
1.76
2.82
1.76
2.82
3.15
5.81
1.79
2.69
170
5.5
65
25
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Clock Cycles
ns (max)
(Limits)
ns (min)
ns (min)
ns (min)
ps rms
Units
MHz
MHz
ns
ns
ns
A
), and