adv7321 Analog Devices, Inc., adv7321 Datasheet
adv7321
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adv7321 Summary of contents
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... PLL CLKIN_B Figure 1. Simplified Functional Block Diagram GENERAL DESCRIPTION The ADV®7320/ADV7321 are high speed, digital-to-analog encoders on single monolithic chips. They include six high speed NSV video D/A converters with TTL compatible inputs. They have separate 8-/10-, 16-/20-, and 24-/30-bit input ports that accept data in high definition and/or standard definition video format ...
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... ADV7320/ADV7321 TABLE OF CONTENTS Specifications..................................................................................... 6 Dynamic Specifications ................................................................... 7 Timing Specifications....................................................................... 8 Timing Diagrams.............................................................................. 9 Absolute Maximum Ratings.......................................................... 16 Thermal Characteristics ............................................................ 16 ESD Caution................................................................................ 16 Pin Configuration and Function Descriptions........................... 17 Typical Performance Characteristics ........................................... 19 MPU Port Description................................................................... 23 Register Access................................................................................ 25 Register Programming............................................................... 25 Subaddress Register (SR7 to SR0) ............................................ 25 Input Configuration ....................................................................... 38 Standard Definition Only.......................................................... 38 Progressive Scan Only or HDTV Only ...
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... Register 0 TR0 = .......................................................................................................80 REVISION HISTORY 10/04—Revision 0: Initial Version Appendix 6—HD Timing ..............................................................81 Appendix 7—Video Output Levels...............................................82 HD YPrPb Output Levels ..........................................................82 RGB Output Levels .....................................................................83 YPrPb Levels—SMPTE/EBU N10............................................84 Appendix 8—Video Standards ......................................................86 Outline Dimensions........................................................................88 Ordering Guide ...........................................................................88 Rev Page ADV7320/ADV7321 ...
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... ADV7320/ADV7321 DETAILED FEATURES High definition programmable features (720p/1080i/1035i) 2× oversampling (148.5 MHz) Internal test pattern generator Color hatch, black bar, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS-A (720p/1080i) Enhanced definition programmable features (525p/625p) 8× ...
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... FILTERS Figure 2. Detailed Functional Block Diagram HDTV: high definition television video, conforming to SMPTE 274M, or SMPTE 296M and SMPTE240M. YCrCb SD, PS component: digital video. YPrPb SD, PS component: analog video. Rev Page ADV7320/ADV7321 DAC PS 8u HDTV 2u DAC DAC RGB DAC ...
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... ADV7320/ADV7321 SPECIFICATIONS V = 2.375 V to 2.625 2.375 V to 2.625 specifications (0°C to 70°C), unless otherwise noted. MIN MAX Table 2. Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity, +ve Differential Nonlinearity, 2 −ve DIGITAL OUTPUTS Output Low Voltage Output High Voltage, V ...
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... Degrees 0 ±% 96.7 ±% −1.0 ns 0.2 ± 75.3 dB 0.25 % 0.2 Degrees 63.5 dB 77.7 dB Rev Page ADV7320/ADV7321 = 3040 Ω 300 Ω. All SET LOAD Test Conditions Luma ramp unweighted Flat field full bandwidth Referenced to 40 IRE NTSC NTSC Luma ramp Flat field full bandwidth ...
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... ADV7320/ADV7321 TIMING SPECIFICATIONS V = 2.375 V to 2.625 2.375 V to 2.625 specifications (0°C to 70°C), unless otherwise noted. MIN MAX Table 4. Parameter MPU PORT 1 SCLOCK Frequency SCLOCK High Pulse Width SCLOCK Low Pulse Width Hold Time (Start Condition), t ...
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... Figure 4. HD Only 4:4:4 Input Mode (Input Mode 010); PS Only 4:4:4 Input Mode (Input Mode 001 Cb0 Cr0 Cb2 Cr2 Cb1 Cb2 Cb3 Cb0 t 11 Cr0 Cr1 Cr2 Cr3 Rev Page ADV7320/ADV7321 Y4 Y5 Cr4 Cb4 Cb4 Cb5 Cr4 Cr5 ...
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... ADV7320/ADV7321 CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 S9–S0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 CLKIN_B* P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME ...
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... USED IN THIS PS ONLY MODE Cb0 NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT Cb2 Cr2 Cb4 Cr4 Cr0 Y1 Cb1 Rev Page ADV7320/ADV7321 Cr0 Cr0 HD INPUT SD INPUT ...
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... ADV7320/ADV7321 CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Cb0 t 11 CLKIN_A S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 Figure 11. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode (Input Mode 011) CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Cb0 t 11 CLKIN_A S_HSYNC, CONTROL S_VSYNC, ...
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... CONTROL OUTPUTS *SELECTED BY ADDRESS 0x01 BIT 7 Figure 14. 20-/16-Bit SD Only Pixel Input Mode (Input Mode 000 Cr4 Cb2 Cr2 Cb4 Cr0 Cb2 Rev Page ADV7320/ADV7321 IN SLAVE MODE IN MASTER/SLAVE MODE IN SLAVE MODE Y3 Cr2 IN MASTER/SLAVE MODE ...
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... ADV7320/ADV7321 Y OUTPUT P_HSYNC P_VSYNC P_BLANK Y9–Y0 C9–C0 a AND b AS PER RELEVANT STANDARD c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC IN TO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY ...
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... S9–S0/Y9–Y0* *SELECTED BY ADDRESS 0x01 BIT 7 Figure 17. SD Timing Input for Timing Mode SDA t 6 SCLK t 2 Figure 18. MPU Port Timing Diagram PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES Rev Page ADV7320/ADV7321 ...
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... JC 260°C θ = 47°C/W JA The ADV7320/ADV7321 is a Pb-free environmentally friendly product manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications and is able to withstand surface-mount soldering up to 255°C (±5°C). ...
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... The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2. Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB is set up on C2. Rev Page ADV7320/ADV7321 48 S_BLANK 47 ...
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... SD or Progressive Scan/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2. This input resets the on-chip timing generator and sets the ADV7320/ADV7321 into default register setting. RESET is an active low signal. ...
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... FREQUENCY (MHz) Figure 22. PS—Y 8× Oversampling Filter 140 160 180 200 140 160 180 200 140 160 180 200 Rev Page ADV7320/ADV7321 Y PASS BAND IN PS OVERSAMPLING MODE 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3 FREQUENCY (MHz) Figure 23. PS— ...
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... ADV7320/ADV7321 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 26. Luma NTSC Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 27. Luma PAL Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – ...
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... Figure 37. Chroma 3.0 MHz Low-Pass Filter Rev Page ADV7320/ADV7321 FREQUENCY (MHz) Figure 35. Luma CIF Low-Pass Filter FREQUENCY (MHz) Figure 36. Luma QCIF Low-Pass Filter ...
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... ADV7320/ADV7321 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 38. Chroma 2.0 MHz Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 39. Chroma 1.3 MHz Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – ...
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... ADV7320/ ADV7321. Each slave device is recognized by a unique address. The ADV7320/ADV7321 have four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 44 ...
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... ADV7320/ADV7321 SDATA SCLOCK WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER S 9 1–7 9 1– START ADRR R/W ACK SUBADDRESS ACK Figure 46. Bus Data Transfer SUBADDR A(S) DATA A(S) LSB = 1 SUBADDR A(S) S SLAVE ADDR A(S) A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER Figure 47 ...
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... REGISTER ACCESS The MPU can write to or read from all registers of the ADV7320/ADV7321 except the subaddress registers, which are write only registers. The subaddress register determines which register the next read or write operation will access. All communication with the part through the bus starts with an access to the subaddress register ...
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... ADV7320/ADV7321 Table 8. Registers 0x02 to 0x0F SR7– SR0 Register Bit Description 0x02 Mode Register 0 Reserved Test Pattern Black Bar Manual RGB Matrix Adjust Sync on RGB 1 RGB/YPrPb Output SD Sync HD Sync 0x03 RGB Matrix 0 0x04 RGB Matrix 1 0x05 RGB Matrix 2 0x06 RGB Matrix 3 ...
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... Rev Page ADV7320/ADV7321 Bit 1 Bit 0 Register Setting Note 0 0 EIA770.2 output 0 1 EIA770.1 output 1 0 Output levels for full input range 1 1 Reserved HSYNC , VSYNC , BLANK EAV/SAV codes SMPTE 293M, ITU- ...
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... ADV7320/ADV7321 Table 10. Register 0x12 SR7– SR0 Register Bit Description 0x12 HD Mode HD Y Delay with Respect Register 3 to Falling Edge of HSYNC HD Color Delay with Respect to Falling Edge of HSYNC HD CGMS HD CGMS CRC Table 11. Registers 0x13 to 0x14 SR7– SR0 Register Bit Description ...
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... Bit 5 Bit 4 Bit 3 Bit Rev Page ADV7320/ADV7321 Bit 1 Bit 0 Register Setting 0 0 must be written to this bit. 0 Disabled. 1 Enabled. Disabled. Enabled. DAC E = Pb; DAC F = Pr. DAC E = Pr; DAC F = Pb. Gamma Curve A. Gamma Curve B. Disabled. Enabled. ...
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... ADV7320/ADV7321 Table 13. Registers 0x16 to 0x37 SR7– SR0 Register Bit Description 0x16 HD Y Level 1 0x17 Level 0x18 Level 0x19 Reserved 0x1A Reserved 0x1B Reserved 0x1C Reserved 0x1D Reserved 0x1E Reserved 0x1F Reserved 0x20 HD Sharpness Filter Gain Value A HD Sharpness ...
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... Rev Page ADV7320/ADV7321 Register Bit 2 Bit 1 Bit 0 Setting Gain Gain … … … … Gain Gain A = −8 … … ...
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... ADV7320/ADV7321 Table 15. Registers 0x3E to 0x43 SR7– SR0 Register Bit Description 0x3E Reserved 0x3F Reserved 0x40 SD Mode Register 0 SD Standard SD Luma Filter SD Chroma Filter 0x41 Reserved 0x42 SD Mode Register 1 SD PrPb SSAF SD DAC Output 1 SD DAC Output 2 SD Pedestal SD Square Pixel ...
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... Rev Page ADV7320/ADV7321 Bit 1 Bit 0 Register Setting 0 Disabled 1 VSYNC = 2.5 lines (PAL), VSYNC = 3 lines (NTSC) 0 Genlock disabled 1 Subcarrier Reset 0 Timing Reset 1 RTC enabled 720 pixels 710 (NTSC)/702 (PAL) Chroma enabled Chroma disabled ...
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... ADV7320/ADV7321 Table 17. Registers 0x4A to 0x58 SR7– SR0 Register Bit Description 0x4A SD Timing SD Slave/Master Register 0 Mode SD Timing Mode SD BLANK Input SD Luma Delay SD Min. Luma Value SD Timing Reset 0x4B SD Timing SD HSYNC Width Register 1 SD HSYNC to VSYNC Delay SD HSYNC to VSYNC Rising Edge Delay ...
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... Rev Page ADV7320/ADV7321 Bit 1 Bit 0 Register Setting 17 16 CGMS Data Bits C19 to C16 Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 9 8 CGMS Data Bits C13 to C8, or WSS Data Bits C13 to C8 ...
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... ADV7320/ADV7321 Table 19. Registers 0x65 to 0x7C SR7– SR0 Register Bit Description 0x65 SD DNR 2 DNR Input Select DNR Mode DNR Block Offset 0x66 SD Gamma A SD Gamma Curve A Data Points 0x67 SD Gamma A SD Gamma Curve A Data Points 0x68 SD Gamma A SD Gamma Curve A Data Points ...
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... Rev Page ADV7320/ADV7321 Bit 1 Bit 0 Register Setting ...
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... Pins S9 to S0, with S0 being the LSB. Using 8-bit input format, the data is input on Pins S9 to S2. The clock input for SD must be input on CLKIN_A, and the clock input for HD must be input on CLKIN_B. Synchronization signals are Rev Page MPEG2 ADV7320/ DECODER ADV7321 27MHz YCrCb CLKIN_A Cb 10 C[9:0] Cr ...
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... WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE. Figure 56. Input Sequence in PS Bit Interleaved Mode (EAV/SAV) MPEG2 DECODER 27MHz OR 54MHz YCrCb INTERLACED YCrCb TO PROGRESSIVE Figure 57. 10-Bit MHz or 54 MHz Rev Page ADV7320/ADV7321 XY Cb0 Y0 Cr0 Cb0 Y1 Cr0 00 XY Cb0 Y0 Cr0 Y1 ADV7320/ ADV7321 CLKIN_A 10 Y[9:0] P_VSYNC, 3 P_HSYNC, P_BLANK ...
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... ADV7320/ADV7321 Table 22. Input Configurations Input Format Total Bits ITU-R BT.656 (See Table 21 Only 8 (27 MHz clock) 10 (27 MHz clock) 8 (54 MHz clock) 10 (54 MHz clock HDTV Only RGB 24 30 ITU-R BT.656 and PS 8 (SD) 8 (PS) ITU-R BT ...
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... N/A 0 N/A 1 N/A 0 N/A 1 N/A HD/PS Color Swap 0x15, Bit 3 DAC A DAC B 0 CVBS Luma 1 CVBS Luma 0 CVBS Luma 1 CVBS Luma Rev Page ADV7320/ADV7321 DAC C DAC D DAC E DAC F Chroma CVBS Luma Chroma Chroma CVBS Luma Chroma Chroma CVBS ...
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... Bits 3 and 2] For any input data that does not conform to the standards selectable in input mode, Subaddress 0x10, asynchronous timing mode can be used to interface to the ADV7320/ADV7321. Timing control signals for HSYNC , VSYNC , and BLANK must be programmed by the user. Macrovision and programmable oversampling rates are not available in async timing mode ...
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... SD REAL-TIME CONTROL, SUBCARRIER RESET, AND TIMING RESET [Subaddress 0x44, Bits 2 and 1] Together with the RTC_SCR_TR pin and SD Mode Register 3 [Address 0x44, Bits 1 and 2], the ADV7320/ADV7321 can be used in (a) timing reset mode, (b) subcarrier phase reset mode, or (c) RTC mode timing reset is achieved in a low-to-high transition on the RTC_SCR_TR pin (Pin 31) ...
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... RTC TIME SLOT 01 NOTES 1 i.e., VCR OR CABLE 2 F PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7320/ADV7321 F SC PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7320/ADV7321 SEQUENCE BIT PAL LINE NORMAL LINE INVERTED NTSC CHANGE ...
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... RESET SEQUENCE A reset is activated with a high-to-low transition on the RESET pin (Pin 33) according to the timing specifications, and the ADV7320/ADV7321 reverts to the default output configuration. Figure 63 illustrates the RESET timing sequence. SD VCR FF/RW SYNC [Subaddress 0x42, Bit 5] In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, i ...
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... The subcarrier register value is divided into 4 F shown above. To load the value into the encoder, users must write to the F registers in sequence, starting with F SC value is not loaded until the F Note that the ADV7320/ADV7321 power-up value for F 0x1E. For precise NTSC F Rev Page Register periods in ...
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... ANCILLARY DATA (HANC) 4 CLOCK 272 CLOCK 4 CLOCK 344 CLOCK Figure 64. EAV/SAV Embedded Timing Figure 65. Active Pixel Timing Rev Page ADV7320/ADV7321 SAV CODE ...
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... The variation of frequency responses are shown in Figure 32 and Figure 33. In addition to the chroma filters listed in Table 27, the ADV7320/ADV7321 contains an SSAF filter specifically designed for the color difference component outputs, U and V. This filter has a cutoff frequency of about 2.7 MHz and a gain of – ...
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... When the manual RGB matrix adjust feature is enabled, the default values in Registers 0x05 to 0x09 are correct for HDTV color space only. The color components are converted according to the 1080i and 720p standards (SMPTE 274M, SMPTE 296M): Rev Page ADV7320/ADV7321 Y Value Cr Value 235 (EB) 128 (80) 16 (10) ...
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... When the manual RGB matrix adjust feature is not enabled, the ADV7320/ADV7321 automatically scales YCrCb inputs to all standards supported by this part as selected by the input mode Register 0x01 [6:4]. SD Luma and Color Control [Subaddresses 0x5C, 0x5D, 0x5E, 0x5F Scale Scale, and SD Cb Scale are three 10-bit-wide control registers that scale the Y, Cb, and Cr output levels ...
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... These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7320/ADV7321 provides a range of ±22.5° increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits (respectively) of adjustment attainable ...
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... ADV7320/ADV7321 SD Brightness Detect [Subaddress 0x7A] The ADV7320/ADV7321 allow monitoring the brightness level of the incoming video data. Brightness detect is a read-only register. Double Buffering [Subaddress 0x13, Bit 7; Subaddress 0x48, Bit 2] Double buffered registers are updated once per field upon the falling edge of the Vsync signal. Double buffering improves the ...
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... Considering the curve to have a total length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed. Rev Page ADV7320/ADV7321 % Gain Note 7.5000% 7.3820% 7 ...
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... ADV7320/ADV7321 For the length 240, the gamma correction curve has to be calculated as follows γ where gamma corrected output x = linear input signal γ = gamma power factor To program the gamma correction registers, calculate the seven values for y using the following formula: ª ...
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... HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS [Subaddresses 0x20, 0x38 to 0x3D] There are three filter modes available on the ADV7320/ ADV7321: sharpness filter mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in Figure 73, the HD sharpness filter must be enabled and the HD adaptive filter enable must be disabled ...
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... ADV7320/ADV7321 HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in Figure 74. Input data was generated by an external signal source. ...
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... It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the DNR block offset. The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing. Rev Page ADV7320/ADV7321 ...
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... ADV7320/ADV7321 DNR MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER NOISE SIGNAL PATH INPUT FILTER BLOCK FILTER OUTPUT Y DATA THRESHOLD? INPUT FILTER OUTPUT ! THRESHOLD MAIN SIGNAL PATH DNR DNR CONTROL SHARPNESS MODE ...
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... The scaling factors are ×1/8, ×1/2, and ×7/8. All other active video passes through unprocessed. SAV/EAV STEP EDGE CONTROL The ADV7320/ADV7321 have the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing. ...
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... ADV7320/ADV7321 VOLTS IRE:FLT 0 VOLTS IRE:FLT 0.5 0 –2 100 L135 – Figure 83. Address 0x42, Bit 100 L135 – Figure 84. Address 0x42, Bit Rev Page ...
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... I2C_VSYNC _gen_sel (0x14, Bit Rev Page ADV7320/ADV7321 Signal on S_HSYNC Pin Duration Tristate – Pipelined SD HSYNC See Appendix 5—SD Timing Modes Pipelined Ext HD/ED HSYNC As per HSYNC timing Pipelined HD/ED HSYNC Same as line blanking interval based on AV code H bit ...
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... AD8061. More information on line driver buffering circuits is given in the relevant op amps’ data sheets. An optional analog reconstruction low-pass filter (LPF) may be required as an anti-imaging filter if the ADV7320/ADV7321 are connected to devices that require this filtering. The filter specifications vary with the application. ...
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... The ADV7320/ADV7321 are optimally designed for lowest noise performance of both radiated and conducted noise. To complement the excellent noise performance of the ADV7320/ ADV7321 imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7320/ ADV7321 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling ...
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... ADV7320/ADV7321 to minimize reflections. For optimum performance recommended that all decoupling and external components relating to the ADV7320/ADV7321 are located on the same side of the PCB and as close as possible to the ADV7320/ADV7321. Any unused inputs should be tied to ground. V ...
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... CGMS data is output on odd and even fields. CGMS data can be transmitted only when the ADV7320/ADV7321 is configured in NTSC mode. The CGMS data is 20 bits long. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit; see Figure 94 ...
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... ADV7320/ADV7321 +700mV 70% r 10% 0mV –300mV 5 0. PEAK WHITE 500mV r 25mV SYNC LEVEL 5.5Ps r 0.125Ps +100 IRE +70 IRE 0 IRE –40 IRE 11.2Ps REF C10 C11 C12 21 0. Figure 92. Progressive Scan 525p CGMS Waveform (Line 41) ...
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... C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 T r 30ns 22. 210ns 22T T = 1/( HORIZONTAL SCAN FREQUENCY H 1H Figure 96. HDTV 1080i CGMS Waveform Rev Page ADV7320/ADV7321 CRC SEQUENCE u 1650/58) = 781.93ns CRC SEQUENCE u 2200/77) = 1.038 P s ...
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... ADV7320/ADV7321 APPENDIX 2—SD WIDE SCREEN SIGNALING [Subaddresses 0x59, 0x5A, 0x5B] The ADV7320/ADV7321 support wide screen signaling (WSS) conforming to the ETS 300 294 standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long, and the function of each of these bits is shown in Table 40 ...
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... FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA608 describe the closed captioning information for Line 21 and Line 284. The ADV7320/ADV7321 use a single buffering method. This means that the closed captioning buffer is only 1 byte deep; therefore, there will be no frame delay in outputting the closed captioning data, unlike other 2-byte-deep buffering systems ...
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... ADV7320/ADV7321 APPENDIX 4—TEST PATTERNS The ADV7320/ADV7321 can generate SD and HD test patterns CH2 200mV M 10.0Ps 30.6000Ps T Figure 99. NTSC Color Bars T 2 CH2 200mV M 10.0Ps T 30.6000Ps Figure 100. PAL Color Bars T 2 CH2 100mV M 10.0Ps T 1.82380ms Figure 101. NTSC Black Bar (–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV,18 mV, 23 mV) ...
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... Figure 106. 625p Field Pattern T 2 EVEN (−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV EVEN (−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 5 mV) Rev Page ADV7320/ADV7321 CH2 100mV M 4.0Ps CH2 EVEN T 1.82936ms Figure 107. 525p Black Bar CH2 100mV M 4.0Ps ...
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... ADV7320/ADV7321 The register settings in Table 41 are used to generate an SD NTSC CVBS output on DAC A, S-video on DACs B and C, and YPrPb on DACs D, E, and F. Upon power-up, the subcarrier registers are programmed with the appropriate values for NTSC. All other registers are set as normal/default. Table 41. NTSC Test Pattern Register Writes ...
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... MODE 0 (CCIR-656)—SLAVE OPTION (TIMING REGISTER 0 TR0 = The ADV7320/ADV7321 are controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...
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... ADV7320/ADV7321 MODE 0 (CCIR-656)—MASTER OPTION (TIMING REGISTER 0 TR0 = The ADV7320/ADV7321 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on S_HSYNC , the V bit is output on S_BLANK , and the F bit is output on S_VSYNC ...
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... ODD FIELD EVEN FIELD F ANALOG VIDEO VERTICAL BLANK VERTICAL BLANK 318 314 315 316 317 319 Figure 111. SD Master Mode 0, PAL Figure 112. SD Master Mode 0, Data Transitions Rev Page ADV7320/ADV7321 DISPLAY DISPLAY 334 335 336 320 ...
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... ADV7320/ADV7321 MODE 1—SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624 ...
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... MODE 1—MASTER OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624 ...
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... ADV7320/ADV7321 MODE 2— SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field ...
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... MODE 2—MASTER OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field ...
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... MODE 3—MASTER/SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7320/ADV7321 accept or generate hori- zontal sync and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624 ...
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... P_VSYNC P_HSYNC VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 122. 1080i HSYNC and VSYNC Input Timing Rev Page ADV7320/ADV7321 DISPLAY 560 DISPLAY 570 583 584 585 1123 ...
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... ADV7320/ADV7321 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 123. EIA 770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 64 Figure 124. EIA 770.1 Standard Output Signals (525p/625p) ...
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... Figure 128. PS RGB Output Levels—RGB Sync Enabled 525mV 525mV Figure 129. SD RGB Output Levels—RGB Sync Disabled 300mV 525mV 300mV 525mV 300mV Figure 130. SD RGB Output Levels—RGB Sync Enabled Rev Page ADV7320/ADV7321 700mV 525mV 300mV 700mV 525mV 300mV 700mV 525mV 300mV 700mV ...
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... ADV7320/ADV7321 YPrPb LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV Figure 131. Pb Levels—NTSC 700mV Figure 132. Pb Levels—PAL 700mV Figure 133. Pr Levels—NTSC 700mV Figure 134. Pr Levels—PAL 700mV 300mV Figure 135. Y Levels—NTSC 700mV 300mV Figure 136. Y Levels—PAL ...
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... LINE PAL NO FILTERING SLOW CLAMP TO 0. VOLTS 0 APL NEEDS SYNC SOURCE. 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. Rev Page ADV7320/ADV7321 L608 MICROSECONDS PRECISION MODE OFF NO FILTERING SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED Figure 140 ...
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... ADV7320/ADV7321 APPENDIX 8—VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE F 0 INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 SAV/EAV: LINE 1–20; 561–583; 1124–1125 SAV/EAV: LINE 21–560; 584–1123 ...
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... VERTICAL BLANK 566 567 568 569 570 583 Rev Page ADV7320/ADV7321 ACTIVE VIDEO ACTIVE VIDEO DISPLAY 26 27 744 745 DISPLAY 560 21 22 DISPLAY 584 585 1123 ...
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... ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADV7320KSTZ 0°C to 70°C 1 ADV7321KSTZ 0°C to 70°C EVAL-ADV7320EB EVAL-ADV7321EB Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05067–0–10/04(0) 0.75 1.60 0.60 MAX 0.45 ...