adv7321 Analog Devices, Inc., adv7321 Datasheet - Page 23

• Manufacturer Part Number: adv7321
• Description: Multiformat 216 Mhz Video Encoder With Six Nsv 12-bit Dacs
• Manufacturer: Analog Devices, Inc.

MPU PORT DESCRIPTION
The ADV7320/ADV7321 support a 2-wire serial (I
compatible) microprocessor bus driving multiple peripherals.
This port operates in an open-drain configuration. Two inputs,
serial data (SDA) and serial clock (SCL), carry information
between any device connected to the bus and the ADV7320/
ADV7321. Each slave device is recognized by a unique address.
The ADV7320/ADV7321 have four possible slave addresses for
both read and write operations. These are unique addresses for
each device and are illustrated in Figure 44. The LSB sets either
a read or write operation. Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation. A1 is
enabled by setting the ALSB pin of the ADV7320/ADV7321 to
Logic 0 or Logic 1. When ALSB is set to 1, there is greater input
bandwidth on the I
transfers on this bus. When ALSB is set to 0, there is reduced
input bandwidth on the I
less than 50 ns will not pass into the I
mode is recommended for noisy systems.
To control the various devices on the bus, the following
protocol must be followed. First, the master initiates a data
transfer by establishing a start condition, defined by a high-to-
low transition on SDA while SCL remains high. This indicates
that an address/data stream will follow. All peripherals respond
to the start condition and shift the next eight bits (7-bit address
+ R/ W bit). The bits are transferred from MSB down to LSB.
The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This is known as an acknowledge bit. All other devices
withdraw from the bus at this point and maintain an idle
condition. The idle condition is where the device monitors the
SDA and SCL lines waiting for the start condition and the
1
0
Figure 44. ADV7320 Slave Address = 0xD4
Figure 45. ADV7321 Slave Address = 0x54
1
1
2
C lines, which allows high speed data
0
0
2
C lines, which means that pulses of
1
1
0
0
1
1
2
SET UP BY
SET UP BY
ADDRESS
CONTROL
C internal controller. This
ADDRESS
CONTROL
ALSB
ALSB
A1
A1
READ/WRITE
READ/WRITE
CONTROL
0
1
CONTROL
0
1
WRITE
READ
WRITE
READ
X
X
2
C-
Rev. 0 | Page 23 of 88
correct transmitted address. The R/ W bit determines the
direction of the data.
Logic 0 on the LSB of the first byte means that the master will
write information to the peripheral. Logic 1 on the LSB of the
first byte means that the master will read information from the
peripheral.
The ADV7320/ADV7321 act as standard slave devices on the
bus. The data on the SDA pin is eight bits long, supporting the
7-bit addresses plus the R/ W bit. It interprets the first byte as
the device address and the second byte as the starting
subaddress. There is a subaddress auto-increment facility. This
allows data to be written to or read from registers in ascending
subaddress sequence starting at any valid subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one
basis without updating all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, then they
cause an immediate jump to the idle condition. During a given
SCL high period, the user should only issue a start condition, a
stop condition, or a stop condition followed by a start
condition. If an invalid subaddress is issued by the user, the
ADV7320/ADV7321 will not issue an acknowledge and will
return to the idle condition. If the user utilizes the auto-
increment method of addressing the encoder and exceeds the
highest subaddress, the following actions are taken:
x In read mode, the highest subaddress register contents are
x In write mode, the data for the invalid byte is not loaded into
Before writing to the subcarrier frequency registers, it is required
to reset ADV7320/ADV7321 at least once after power-up.
The four subcarrier frequency registers must be updated,
starting with Subcarrier Frequency Register 0 and ending with
Subcarrier Frequency Register 3. The subcarrier frequency will
only update after the last subcarrier frequency register byte has
been received by the ADV7320/ADV7321.
Figure 46 illustrates an example of data transfer for a write
sequence and the start and stop conditions. Figure 47 shows bus
write and read sequences.
output until the master device issues a no acknowledge. This
indicates the end of a read. A no acknowledge condition is
when the SDA line is not pulled low on the ninth pulse.
any subaddress register, a no acknowledge is issued by the
ADV7320/ADV7321, and the part returns to the idle
condition.
ADV7320/ADV7321