adv7321 Analog Devices, Inc., adv7321 Datasheet - Page 25

• Manufacturer Part Number: adv7321
• Description: Multiformat 216 Mhz Video Encoder With Six Nsv 12-bit Dacs
• Manufacturer: Analog Devices, Inc.

REGISTER ACCESS
The MPU can write to or read from all registers of the
ADV7320/ADV7321 except the subaddress registers, which are
write only registers. The subaddress register determines which
register the next read or write operation will access. All
communication with the part through the bus starts with an
access to the subaddress register. A read/write operation is then
performed from/to the target address, which increments to the
next address until a stop command is performed on the bus.
Table 7. Registers 0x00 to 0x01
SR7–
SR0
0x00
0x01
Register
Power
Mode
Register
Mode
Select
Register
Bit Description
Sleep Mode. With this
control enabled, the
current consumption is
reduced to µA level. All
DACs and the internal PLL
cct are disabled. I
registers can be read from
and written to in sleep
mode.
PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the oversampling to be
switched off.
DAC F: Power On/Off.
DAC E: Power On/Off.
DAC D: Power On/Off.
DAC C: Power On/Off.
DAC B: Power On/Off.
DAC A: Power On/Off.
Reserved.
Clock Edge.
Reserved.
Clock Align.
Input Mode.
Y/C/S Bus Swap.
2
C
Bit 7
0
1
0
1
Bit 6
0
1
0
0
0
0
1
1
1
1
Bit 5
0
1
0
0
1
1
0
0
1
1
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Bit 4
0
1
0
1
0
1
0
1
0
1
Bit 3
0
1
0
1
REGISTER PROGRAMMING
The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The communication register is an 8-bit write only register. After
the encoder’s bus is accessed and a read/write operation is
selected, the subaddress is set up. The subaddress register
determines to or from which register the operation takes place.
Bit 2
0
1
0
Bit 1
0
1
0
1
Bit 0
0
1
0
Register Setting
Sleep mode off.
Sleep mode on.
PLL on.
PLL off.
DAC F off.
DAC F on.
DAC E off.
DAC E on.
DAC D off.
DAC D on.
DAC C off.
DAC C on.
DAC B off.
DAC B on.
DAC A off.
DAC A on.
Reserved.
Cb clocked upon rising
edge.
Y clocked upon rising
edge.
Must be set if the phase
delay between the two
input clocks is <9.25 ns
or >27.75 ns.
SD input only.
PS input only.
HDTV input only.
SD and PS (20-bit).
SD and PS (10-bit).
SD and HDTV (SD
oversampled).
SD and HDTV (HDTV
oversampled).
PS only (at 54 MHz).
Allows data to be
applied to data ports in
various configurations
(SD feature only).
ADV7320/ADV7321
Reg. Reset
Values
(Shaded)
0xFC
Only for PS
interleaved
input at 27 MHz.
Only if two
input clocks are
used.
0x38
See Table 21.