adv7322 Analog Devices, Inc., adv7322 Datasheet - Page 39

• Manufacturer Part Number: adv7322
• Description: Multiformat 11-bit Hdtv Video Encoder
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
INPUT CONFIGURATION
Note that the ADV7322 defaults to simultaneous standard
definition and progressive scan upon power-up (Address[0x01]:
Input Mode = 011).
STANDARD DEFINITION ONLY
Address[0x01]: Input Mode = 000
The 8-bit multiplexed input data is input on Pins S7 to S0 (or
Pins Y7 to Y0, depending on Register Address 0x01, Bit 7), with
S0 being the LSB in 8-bit input mode (see Table 21). Input
standards supported are ITU-R BT.601/656. In 16-bit input
mode, the Y pixel data is input on Pins S7 to S0 and CrCb data
is input on Pins Y7 to Y0 (see Table 21).
16-Bit Mode Operation
When Register 0x01 Bit 7 = 0, CrCb data is input on the Y bus
and Y data is input on the S bus. When Register 0x01 Bit 7 = 1,
CrCb data is input on the C bus and Y data is input on Y bus.
The 27 MHz clock input must be input on Pin CLKIN_A. Input
sync signals are input on the S_VSYNC , S_HSYNC , and
S_BLANK pins.
Table 21. SD 8-Bit and 16-Bit Configuration
Parameter
Register 0x01, Bit 7 = 0
Register 0x01, Bit 7 = 1
PROGRESSIVE SCAN ONLY OR HDTV ONLY
Address[0x01]: Input Mode = 001 or 010, Respectively
YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data is
Y Bus
S Bus
C Bus
Y Bus
S Bus
C Bus
*SELECTED BY ADDRESS 0x01 BIT 7
DECODER
MPEG2
YCrCb
Figure 48. SD Only Input Mode
27MHz
8
3
8-Bit Mode
656/601, YCrCb
656/601, YCrCb
S_HSYNC,
S_BLANK
S_VSYNC,
CLKIN_A
S[7:0] OR Y[7:0]*
ADV7322
Configuration
16-Bit Mode
CrCb
Y
Y
CrCb
Rev. PrA | Page 39 of 88
input on Pins Y7 to Y0 and the CrCb data is input on Pins C7 to
C0. In 4:4:4 input mode, Y data is input on Pins Y7 to Y0,
Cb data is input on Pins C7 to C0, and Cr data is input on Pins
S7 to S0. If the YCrCb data does not conform to SMPTE 293M
(525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i], SMPTE
296M[720p], SMPTE 240M(1035i) or BTA-T1004/1362, the
async timing mode must be used. RGB data can only be input in
4:4:4 format in PS input mode or in HDTV input mode when
HD RGB input is enabled. G data is input on Pins Y7 to Y0, R
data is input on Pins S7 to S0, and B data is input on Pins C7 to
C0. The clock signal must be input on Pin CLKIN_A.
SIMULTANEOUS STANDARD DEFINITION AND
PROGRESSIVE SCAN OR HDTV
Address[0x01]: Input Mode 011 (SD 8-Bit, PS 16-Bit) or 101
(SD and HD, SD Oversampled), 110 (SD and HD, HD
Oversampled), Respectively
YCrCb, PS, HDTV, or any other HD data must be input in 4:2:2
format. In 4:2:2 input mode, the HD Y data is input on Pins Y7
to Y0 and the HD CrCb data is input on Pins C7 to C0. If PS
4:2:2 data is interleaved onto a single 10-bit bus, Pins Y7 to Y0
are used for the input port. The input data is to be input at 27
MHz, with the data being clocked on the rising and falling edge
of the input clock. The input mode register at Address 0x01 is
set accordingly. If the YCrCb data does not conform to SMPTE
293M (525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i],
SMPTE 296M[720p], SMPTE 240M(1035i) or BTA-T1004, the
async timing mode must be used.
The 8- bit standard definition data must be compliant with
ITU-R BT.601/656 in 4:2:2 format. Standard definition data is
input on Pins S7 to S0, with S0 being the LSB. The clock input
for SD must be input on CLKIN_A and the clock input for
HD/PS must be input on CLKIN_B. Synchronization signals
are optional. SD syncs are input on Pins S_VSYNC , S_HSYNC ,
and S_BLANK . HD syncs on Pins P_VSYNC , P_HSYNC , and
P_BLANK .
INTERLACED TO
PROGRESSIVE
DECODER
MPEG2
YCrCb
Figure 49. Progressive Scan Input Mode
Cb
Cr
Y
27MHz
8
8
8
3
CLKIN_A
C[7:0]
S[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7322
ADV7322