adv7322 Analog Devices, Inc., adv7322 Datasheet - Page 40

• Manufacturer Part Number: adv7322
• Description: Multiformat 11-bit Hdtv Video Encoder
• Manufacturer: Analog Devices, Inc.

ADV7322
If in simultaneous SD/HD input mode and the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
ALIGN bit [Address 0x01, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
CLKIN_A
CLKIN_B
INTERLACED TO
PROGRESSIVE
DECODER
DECODER
DECODER
YCrCb
MPEG2
t
t
Figure 52. Clock Phase with Two Input Clocks
SDTV
HDTV
DELAY
DELAY
Figure 51. Simultaneous HD and SD Input
Figure 50. Simultaneous PS and SD Input
1080i
1035i
720p
9.25ns OR
! 27.75ns
OR
OR
YCrCb
Y
74.25MHz
CrCb
27MHz
27MHz
CrCb
Y
27MHz
8
8
8
3
3
8
8
8
3
3
P_HSYNC,
S_HSYNC,
S_BLANK
CLKIN_A
S[7:0]
C[7:0]
Y[7:0]
P_VSYNC,
P_BLANK
CLKIN_B
S_VSYNC,
ADV7322
S_VSYNC,
S_HSYNC,
S_BLANK
CLKIN_A
S[7:0]
C[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_B
ADV7322
Rev. PrA | Page 40 of 88
PROGRESSIVE SCAN AT 27 MHZ (DUAL EDGE)
OR 54 MHZ
Address[0x01]: Input Mode 100 or 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or
54 MHz. The input data is interleaved onto a single 8-bit bus
and is input on Pins Y7 to Y0. When a 27 MHz clock is supplied,
the data is clocked in on the rising and falling edge of the input
clock and CLOCK EDGE [Address 0x01, Bit 1] must be set
accordingly.
Table 22 provides an overview of all possible input configurations.
Figure 53, Figure 54, and Figure 55 show the possible conditions:
(a) Cb data on the rising edge; and (b) Y data on the rising edge.
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
PIXEL INPUT
WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
Y7–Y0
Y7–Y0
CLKIN_B
DATA
Figure 53. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
PROGRESSIVE
DECODER
INTERLACED
MPEG2
YCrCb
FF
FF
TO
FF
Figure 56. 10-Bit PS at 27 MHz or 54 MHz
00
00
27MHz OR 54MHz
00
Preliminary Technical Data
YCrCb
00
00
00
XY
XY
8
XY
3
Cb0
Y0
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_A
Y[7:0]
Cb0
ADV7322
Cb0
Y0
Y0
Cr0
Y1
Cr0
Cr0
Y1
Y1