adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 15

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ABSOLUTE MAXIMUM RATINGS
1
ESD SENSITIVITY
TIMING SPECIFICATIONS
The ADSP-21267’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the DSP’s internal clock frequency and exter-
nal (CLKIN) clock frequency with the CLKCFG1-0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
Table 7. ADSP-21267 CLKOUT and CCLK Clock Generation Operation
1
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Junction Temperature under Bias
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21267 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
Timing Requirements
CLKIN
CCLK
Timing Requirements
t
t
t
t
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV)
only, and functional operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CK
CCLK
SCLK
SPICLK
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
1
1
PRELIMINARY TECHNICAL DATA
VDD
DDEXT
DDINT
)
1
)
Description
Input Clock
Core Clock
Description
CLKIN Clock Period
(Processor) Core Clock Period
Serial Port Clock Period = (t
SPI Clock Period = (t
1
)
1
1
-0.3 V to +1.4 V
-0.3 V to +1.4 V
-0.3 V to +3.8 V
-0.5 V to V
-0.5 V to V
200 pF
-65 C to +150 C
125 C
Rev. PrA | Page 15 of 44 | January 2004
CCLK
) x SPIR
DDEXT
DDEXT
CCLK
1
1
+ 0.5 V
+ 0.5 V
) x SR
The ADSP-21267’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control
Calculation
1/t
1/t
CK
CCLK
ADSP-21267
(Table
7).