adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 5

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21267 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wrap-around, reduce
overhead, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21267 can conditionally execute a multiply, an add, and a sub-
tract in both processing elements while branching and fetching
up to four 32-bit values from memory; all in a single instruction.
ADSP-21267 MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21267 adds the following architectural features to
the SIMD SHARC family core:
Dual-Ported On-Chip Memory
The ADSP-21267 contains one megabit of internal SRAM and
three megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory, in combination with three separate on-chip
buses, allow two data transfers from the core and one from the
I/O processor, in a single cycle.
On the ADSP-21267, the SRAM can be configured as a maxi-
mum of 32K words of 32-bit data, 64K words of 16-bit data, 21K
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to one megabit. All of the memory can
be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
DMA Controller
The ADSP-21267’s on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers
can occur between the ADSP-21267’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
port, the IDP (input data port/parallel data acquisition port) or
ADSP-21267 Memory Map on page
PRELIMINARY TECHNICAL DATA
Rev. PrA | Page 5 of 44 | January 2004
6). Each
the parallel port. Eighteen channels of DMA are available on the
ADSP-21267 — one for the SPI interface, eight via the serial
ports, eight via the Input Data Port and one via the processor’s
parallel port. Programs can be downloaded to the ADSP-21267
using DMA transfers. Other DMA features include interrupt
generation upon completion of DMA transfers, and DMA
chaining for automatic linked DMA transfers.
Digital Audio Interface (DAI)
The Digital Audio Interface (DAI) provides the ability to con-
nect various peripherals to any of the DSPs DAI pins
(DAI_P[20:1]).
Programs make these connections using the Signal Routing
Unit (SRU, shown in the block diagram on
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with non-
configurable signal paths.
The DAI also includes 4 serial ports, 2 precision clock genera-
tors (PCG), an input data port (IDP), 6 flag outputs and 6 flag
inputs, and 3 timers. The IDP provides an additional input path
to the ADSP-21267 core, configurable as either eight channels
of I
synchronous parallel data acquisition port Each data channel
has its own DMA channel that is independent from the ADSP-
21267's serial ports.
For complete information on using the DAI, see the ADSP-
2126x SHARC DSP Peripherals Manual.
Serial Ports
The ADSP-21267 features four full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as the AD183x
family of audio codecs, ADCs, and DACs. The serial ports are
made up of two data lines, a clock and frame sync. The data
lines can be programmed to either transmit or receive and each
data line has its own dedicated DMA channel.
Serial ports are enabled via 8 programmable and simultaneous
receive or transmit pins that support up to 16 transmit or 16
receive channels of audio data when all four SPORTS are
enabled, or four full duplex TDM streams of 128 channels per
frame.
The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of 37.5
Mbits/s for a 150 MHz core. Serial port data can be automati-
cally transferred to and from on-chip memory via a dedicated
DMA. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro-
vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.
Serial ports operate in four modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
2
S or serial data or as seven channels plus a single 20-bit wide
ADSP-21267
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1).