adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 2

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21267
KEY FEATURES
At 150 MHz (6.65 ns) core instruction rate, the ADSP-21267
Code compatibility—At assembly level, uses the same
Super Harvard Architecture—three independent buses for
1M Bit on-chip dual-ported SRAM (0.5M Bit in block 0 and
3M Bits on-chip dual-ported mask-programmable ROM (1.5M
Dual Data Address Generators (DAGs) with modulo and bit-
Zero-overhead looping with single-cycle loop setup, provid-
Single Instruction Multiple Data (SIMD) architecture
DMA Controller supports:
Asynchronous parallel/external port provides:
Digital Audio Interface (DAI) includes four serial ports, two
operates at 900 MFLOPS performance whether operating
on fixed or floating point data
300 MMACS sustained performance at 150 MHz
instruction set as other SHARC DSPs
dual data fetch, instruction fetch, and nonintrusive, zero-
overhead I/O
0.5M Bit in block 1) for simultaneous access by core proces-
sor and DMA
Bits in block 0 and 1.5M Bits in block 1)
reverse addressing
ing efficient program sequencing
provides:
Two computational processing elements
Concurrent execution— Each processing element executes
18 zero-overhead DMA channels for transfers between
32-bit background DMA transfers at core clock speed, in
Access to asynchronous external memory
16 multiplexed address/data lines that can support 24-bit
50 Mbyte per sec transfer rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLK
precision clock generators, an input data port/parallel data
acquisition port, three timers and a signal routing unit
the same instruction, but operates on different data
ADSP-21267 internal memory and the four serial ports,
the input data port (IDP) , SPI-compatible port, and the
parallel port
parallel with full-speed processor execution
address external address range with 8-bit data or 16-bit
address external address range with 16-bit data
PRELIMINARY TECHNICAL DATA
Rev. PrA | Page 2 of 44 | January 2004
Serial Ports provide:
Input Data Port provides an additional input path to the DSP
Signal Routing Unit (SRU) provides configurable and flexible
Serial Peripheral Interface (SPI)
Master or slave serial boot through SPI
Full-duplex operation
Master-Slave mode multi-master support
Open drain outputs
Programmable baud rates, clock polarities and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
ROM Based Security features:
PLL has a wide variety of software and hardware multi-
JTAG background telemetry for enhanced emulation
IEEE 1149.1 JTAG standard test access port and on-chip
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages
Four dual data line serial ports that operate at 37.5M Bits/s
Left-justified Sample Pair and I
TDM support for telecommunications interfaces including
Up to 4 full-duplex TDM streams, each with 128 channels
Companding selection on a per channel basis in TDM mode
core configurable as either eight channels of I
data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port
Supports receive audio channel data in I
connections between all DAI components, four serial
ports, three timers, 10 interrupts, six flag inputs, six flag
outputs, two precision clock generators, an input data
port/parallel data acquisition port, and 20 SRU I/O pins
(DAI_Px)
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
plier/divider ratios
features
emulation
Also available in lead-free packages
on each data line —each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair
direction for up to 16 simultaneous receive or transmit
channels using two I
serial port
128 TDM channel support for newer telephony inter-
faces such as H.100/H.110
per frame
sample pair, or right-justified mode
access under program control to sensitive code
2
S compatible stereo devices per
2
S Support, programmable
2
S, Left-justified
2
S or serial