adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 32

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21267
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2126x Hardware Reference Manual. Note
Table 27. Parallel Data Acquisition Port (PDAP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SPCLKEN
HPCLKEN
PDSD
PDHD
PDCLKW
PDCLK
PDHLDD
PDSTRB
27. PDAP is the parallel mode operation of channel 0 of
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
Clock Width
Clock Period
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
PDAP Strobe Pulse Width
(PDAP_STROBE)
(PDAP_CLKEN)
DAI_P[20:1]
DAI_P[20:1]
(PDAP_CLK)
DAI_P[20:1]
PRELIMINARY TECHNICAL DATA
DATA
Rev. PrA | Page 32 of 44 | January 2004
Figure 24. PDAP Timing
t
PDCLKW
1
t
SPCLKEN
1
1
t
PDSD
that the most significant 16 bits of external PDAP data can be
provided through either the parallel port AD[15:0] or the
DAI_P[20:5] pins. The remaining 4 bits can only be sourced
through DAI_P[4:1]. The timing below is valid at the
DAI_P[20:1] pins or at the AD[15:0] pins.
1
t
SAMPLE EDGE
PDHLDD
t
HPCLKEN
t
PDHD
Min
2.5
2.5
2.5
2.5
7
20
2 x t
1 x t
t
PDSTRB
CCLK
CCLK
– 1
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns