dsp56857 Freescale Semiconductor, Inc, dsp56857 Datasheet
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... Data Sheet Technical Data 56800E 16-bit Digital Signal Controllers DSP56857 Rev. 6 01/2007 freescale.com ...
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General Description • 120 MIPS at 120MHz • 40K x 16-bit Program SRAM • 24K x 16-bit Data SRAM • 16-bit Boot ROM • Six (6) independent channels of DMA • Two (2) Enhanced Synchronous Serial Interfaces ...
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Part 1 Overview 1.1 56857 Features 1.1.1 Digital Signal Processing Core • Efficient 16-bit engine with dual Harvard architecture • 120 Million Instructions Per Second (MIPS) at 120MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • • Four ...
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Parallel Host Interface* • Time of Day • GPIO * Each peripheral I/O can be used alternately as a General Purpose I/O if not needed 1.1.4 Energy Information • Fabricated in high-density CMOS with 3.3V, ...
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... Description Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted 56857 Technical Data, Rev. 6 Order Number 56800ERM DSP5685xUM DSP56857 DSP56857E 1 Voltage ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56857 are organized into functional groups, as shown in as illustrated in Figure 2-1. In Table 3-1 present. Table 2-1 Functional Group Pin Allocations Power (V V ...
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Logic Power I/O Power Analog 1 Power Chip CS0 - CS3 (GPIOA0 - A3) Select HD0 - HD7 (GPIOB0 - B7) HA0 - HA2 (GPIOB8 - B10) HRWB (HRD) (GPIOB11) Host HDS (HWR) (GPIOB12) Interface HCS (GPIOB13) HREQ (HTRQ) (GPIOB14) ...
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Part 3 Signals and Package Information All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are enabled by default. Exceptions: 1. When a pin has GPIO functionality, the pull-up may be disabled under software ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 5 V DDIO 6 V DDIO 13 V DDIO 34 V DDIO 45 V DDIO 47 V DDIO 48 V DDIO 53 V DDIO ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 18 V SSA 19 V SSA 55 CS0 Output GPIOA0 Input/Output 56 CS1 Output GPIOA1 Input/Output 57 CS2 Output GPIOA2 Input/Output 58 CS3 Output ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 29 HD3 GPIOB3 Input/Output 30 HD4 GPIOB4 Input/Output 31 HD5 GPIOB5 Input/Output 32 HD6 GPIOB6 Input/Output 33 HD7 GPIOB7 Input/Output 62 HA0 GPIOB8 Input/Output ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 63 HA1 GPIOB9 Input/Output 64 HA2 GPIOB10 Input/Output 65 HRWB HRD GPIOB11 Input/Output 83 HDS HWR GPIOB12 Input/Output 84 HCS GPIOB13 Input/Output Freescale Semiconductor ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 85 HREQ Open Drain Output HTRQ Open Drain Output GPIOB14 Input/Output 86 HACK HRRQ Open Drain Output GPIOB15 Input/Output 81 TIO0 Input/Output GPIOG0 Input/Output ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 77 TIO3 Input/Output GPIOG3 Input/Output 15 IRQA 16 IRQB 10 MODE A GPIOH0 Input/Output 11 MODE B GPIOH1 Input/Output 12 MODE C GPIOH2 Input/Output ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 52 TXD0 Output(Z) GPIOE1 Input/Output 74 RXD1 GPIOE2 Input/Output 75 TXD1 Output(Z) GPIOE3 Input/Output 92 STD0 Output GPIOC0 Input/Output 93 SRD0 GPIOC1 Input/Output 94 ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 96 SC01 Input/Output GPIOC4 Input/Output 97 SC02 Input/Output GPIOC5 Input/Output 66 STD1 Output GPIOD0 Input/Output 67 SRD1 GPIOD1 Input/Output 68 SCK1 Input/Output GPIOD2 Input/Output ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 70 SC11 Input/Output GPIOD4 Input/Output 71 SC12 Input/Output GPIOD5 Input/Output 1 MISO Input/Output GPIOF0 Input/Output 2 MOSI Output (Z) GPIOF1 Input/Output 18 Type ESSI ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 3 SCK Input/Output GPIOF2 Input/Output 4 SS GPIOF3 Input/Output 20 XTAL Input/Output 21 EXTAL 26 CLKO Output 44 TCK 42 TDI 41 TDO Output(Z) ...
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Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued) Pin No. Signal Name 40 TRST 39 DE Input/Output 20 Type Input Test Reset (TRST)—As an input, a low signal on this pin provides a reset signal to ...
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Part 4 Specifications 4.1 General Characteristics The 56857 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand ...
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Table 4-1 Absolute Maximum Ratings Characteristic Supply voltage, core Supply voltage, IO Supply voltage, analog Digital input voltages Analog input voltages (XTAL, EXTAL) Current drain per pin excluding V Junction temperature Storage temperature range 1. V must not exceed V ...
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Characteristic Thermal resistance junction-to-ambient (estimated) I/O pin power dissipation Power dissipation Maximum allowed See Section 6.1 for more detail Junction Temperature TA = Ambient Temperature 4.2 DC Electrical Characteristics Table 4-4 DC Electrical Characteristics ...
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Table 4-4 DC Electrical Characteristics (Continued) Operating Conditions SSIO SSA Characteristic V supply current (I/O circuity) DDIO 5 Run 2 Deep Stop V supply current (analog circuity) DDA 2 Deep Stop 6 Low Voltage ...
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Supply Voltage Sequencing and Separation Cautions Figure 4-2 shows two situations to avoid in sequencing the V 3.3V 1. Note rising before DDIO DDA rising much faster ...
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AC Electrical Characteristics Timing waveforms in Section 4.4 all pins except XTAL, which is tested using the input levels in and V for an input signal are shown. IL Input Signal Midpoint1 Fall Time Note: The midpoint is V ...
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External Clock Operation The 56857 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL ...
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Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL Table 4-5 External Clock Operation Timing Requirements Operating Conditions SSIO SSA Characteristic Frequency of operation (external clock driver) 4 Clock Pulse Width 2, ...
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Operating Conditions SSIO SSA Characteristic External reference crystal frequency for the PLL PLL output frequency 2 PLL stabilization time 1. An externally supplied reference clock should be as free as possible from any phase ...
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RESET Figure 4-10 Asynchronous Reset Timing IRQA IRQB Figure 4-11 External Interrupt Timing (Negative-Edge-Sensitive) General Purpose I/O Pin t IG IRQA, IRQB Figure 4-12 External Level-Sensitive Interrupt Timing t IW IRQA Figure 4-13 Recovery from Stop State Using Asynchronous Interrupt ...
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Host Interface Port Table 4-8 Host Interface Port Timing Operating Conditions SSIO SSA Characteristic Access time Disable time Time to disassert Lead time Access time Disable time Disable time Setup time Hold time ...
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HACK HD HREQ Figure 4-15 Controller-to-Host DMA Read Model HA HCS HDS HRW HD Figure 4-16 Single Strobe Read Mode HA HCS HWR HRD HD 32 TACKDZ TACKDV TREQACKL TACKREQH TRADV TRADV Figure 4-17 Dual Strobe Read Mode 56857 Technical ...
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HACK HD HREQ Figure 4-18 Host-to-Controller DMA Write Mode HA HCS HDS HRW HD Figure 4-19 Single Strobe Write Mode HA HCS HWR HRD HD Freescale Semiconductor TDACKS TREQACKL TACKREQH TWDS TADSS TADSS TWDS TADSS TADSS Figure 4-20 Dual Strobe ...
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Serial Peripheral Interface (SPI) Timing Operating Conditions SSIO SSA Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCLK) high time Master Slave Clock (SCLK) low ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 4-21 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref) t ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 4-23 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...
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Quad Timer Timing Operating Conditions SSIO SSA Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. In the formulas listed clock cycle. For f ...
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Table 4-11 ESSI Master Mode Operating Conditions SSIO SSA Parameter Delay from SCK high to SC2 (bl) high - Master Delay from SCK high to SC2 (wl) high - Master Delay from SC0 high ...
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SCKH SCK output SC2 (bl) output t SC2 (wl) output t TXVM STD SC0 output t RFSBHM SC1 (bl) output t RFSWHM SC1 (wl) output t SRD Figure 4-26 Master Mode Timing Diagram Table 4-12 ESSI Slave Mode Operating ...
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Table 4-12 ESSI Slave Mode Operating Conditions SSIO SSA Parameter Delay from SC0 high to SC1 (bl) high - Slave Delay from SC0 high to SC1 (wl) high - Slave Delay from SCK high ...
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SCKH SCK input t SC2 (bl) input t TFSWHS SC2 (wl) input t FTXES t TXVS t TXES STD SC0 input t RFSBHS SC1 (bl) input t RFSWHS SC1 (wl) input t SS SRD Figure 4-27 Slave Mode Clock ...
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RXD SCI receive data pin (Input) TXD SCI receive data pin (Input) 4.12 JTAG Timing Operating Conditions SSIO SSA Characteristic 2 TCK frequency of operation TCK cycle time TCK clock pulse width TMS, TDI ...
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TCK (Input – Figure 4-30 Test Clock Input Timing Diagram TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 4-31 Test Access Port Timing Diagram TRST ...
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GPIO Timing Operating Conditions SSIO SSA Characteristic GPIO input period GPIO input high/low period GPIO output period GPIO output high/low period 1. In the formulas listed clock cycle. For f 2. ...
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Part 5 Packaging 5.1 Package and Pin-Out Information 56857 This section contains package and pin-out information for the 100-pin LQFP configuration of the 56857. MISO MOSI SCK PIN DDIO V DDIO V SSIO ...
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Table 5-1 56857 Pin Identification By Pin Number Pin No. Signal Name Pin No. 1 MISO 2 MOSI 3 SCK DDIO 6 V DDIO 7 V SSIO MODA 11 ...
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S 0.15 (0.006) S -T- - 0.15 (0.006 -AB- (24X PER SIDE ° 0.25 (0.010 GAUGE PLANE W Q ° DETAIL AD Figure 5-2 100-pin LQPF Mechanical Information Please ...
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Part 6 Design Considerations 6.1 Thermal Design Considerations An estimation of the chip junction temperature, T Equation Where ambient temperature ° package junction-to-ambient thermal resistance °C/W θJA ...
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As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection ...
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Take special care to minimize noise levels on the V • When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device. • Designs that utilize the TRST pin for JTAG ...
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... Part Voltage DSP56857 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) DSP56857 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) *This package is RoHS compliant. Freescale Semiconductor Pin Package Type Count 100 100 56857 Technical Data, Rev. 6 Electrical Design Considerations Frequency Order Number (MHz) 120 DSP56857BU120 120 DSP56857BUE * 51 ...
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Technical Data, Rev. 6 Freescale Semiconductor ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56857 Rev. 6 01/2007 ...