dsp56857 Freescale Semiconductor, Inc, dsp56857 Datasheet - Page 18

• Manufacturer Part Number: dsp56857
• Description: Dsp56857 Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

18
Pin No.
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
70
71
1
2
Signal Name
GPIOD4
GPIOD5
GPIOF0
GPIOF1
SC11
SC12
MISO
MOSI
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output (Z)
Input/
Type
56857 Technical Data, Rev. 6
ESSI Serial Control Pin 1 (SC11)—The function of this pin is determined
by the selection of either synchronous or asynchronous mode. For
asynchronous mode, this pin is the receiver frame sync I/O. For
synchronous mode, this pin is used either for transmitter2 output or for
serial I/O flag 1.
Port D GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
ESSI Serial Control Pin 2 (SC12)—This pin is used for frame sync I/O.
SC02 is the frame sync for both the transmitter and receiver in
synchronous mode and for the transmitter only in asynchronous mode.
When configured as an output, this pin is the internally generated frame
sync signal. When configured as an input, this pin receives an external
frame sync signal for the transmitter (and the receiver in synchronous
operation).
Port D GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when the
ESSI is not in use.
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected. The driver on this pin can be configured as an open-drain
driver by the SPI’s Wired-OR mode (WOM) bit when this pin is configured
for SPI operation.
Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places
data on the MOSI line a half-cycle before the clock edge that the slave
device uses to latch the data. The driver on this pin can be configured as
an open-drain driver by the SPI’s WOM bit when this pin is configured for
SPI operation.
Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as input or output pin.
Description
Freescale Semiconductor