dsp56857 Freescale Semiconductor, Inc, dsp56857 Datasheet - Page 15

• Manufacturer Part Number: dsp56857
• Description: Dsp56857 Digital Signal Controller
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Pin No.
Table 3-1 56857 Signal and Package Information for the 100-pin LQFP (Continued)
77
15
16
10
11
12
28
27
51
Signal Name
MODE A
MODE B
MODE C
GPIOG3
GPIOH0
GPIOH1
GPIOH2
GPIOE0
RESET
RSTO
RXD0
IRQA
IRQB
TIO3
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input
Input
Input
Input
Type
Input
Input
56857 Technical Data, Rev. 6
Timer Input/Output (TIO3)—This pin can be independently configured to
be either a timer input source or an output flag.
Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as an input or output pin.
External Interrupt Request A and B—The IRQA and IRQB inputs are
asynchronous external interrupt requests that indicate that an external
device is requesting service. A Schmitt trigger input is used for noise
immunity. They can be programmed to be level-sensitive or
negative-edge- triggered. If level-sensitive triggering is selected, an
external pull-up resistor is required for Wired-OR operation.
Mode Select (MODE A)—During the bootstrap process MODE A selects
one of the eight bootstrap modes.
Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
Mode Select (MODE B)—During the bootstrap process MODE B selects
one of the eight bootstrap modes.
Port H GPIOH1—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
Mode Select (MODE C)—During the bootstrap process MODE C selects
one of the eight bootstrap modes.
Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after the
bootstrap process has completed.
Reset (RESET)—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity. When
the RESET pin is deasserted, the initial chip operating mode is latched
from the MODE A, MODE B, and MODE C pins.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary not to
reset the JTAG/Enhanced OnCE module. In this case, assert RESET, but
do not assert TRST.
Reset Output (RSTO)—This output is asserted on any reset condition
(external reset, low voltage, software or COP).
Serial Receive Data 0 (RXD0)—This input receives byte-oriented serial
data and transfers it to the SCI 0 receive shift register.
Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that can
individually be programmed as input or output pin.
Description
Introduction
15