mc33976 Freescale Semiconductor, Inc, mc33976 Datasheet - Page 10

• Manufacturer Part Number: mc33976
• Description: Dual Gauge Driver With Configurable Response Time
• Manufacturer: Freescale Semiconductor, Inc

Interface (SPI) controlled, dual step motor gauge driver
integrated circuit (IC). This monolithic IC consists of four dual
output H-Bridge coil drivers and the associated control logic.
Each pair of H-Bridge drivers is used to automatically control
the speed, direction, and magnitude of current through the
two coils of a two-phase instrumentation step motor, similar
H-BRIDGE OUTPUTS 0 (COS0+, COS0-, SIN0+,
SIN0-)
source or sink current. The H-Bridge pins linearly drive the
sine and cosine coils of two separate step motors to provide
four-quadrant operation.
GROUND (GND)
side output transistors as well as the logic portion of the
device. They also help dissipate heat from the device.
CHIP SELECT (CS)
device. When this pin is in a logic [0] state, the 33976 is
capable of transferring information to, and receiving
information from, the master. The 33976 latches data in from
the Input Shift registers to the addressed registers on the
rising edge of
when
SCLK and SI pins are ignored and the SO pin is tri-stated
(high impedance).
state to a logic [0] state when SCLK is a logic [0].
internal pull-up (l
section of the Static Electrical Characteristics table entitled
CONTROL
SERIAL CLOCK (SCLK)
device. The SI pin accepts data into the Input Shift register on
the falling edge of the SCLK signal, while the Serial Output
pin (SO) shifts data information out of the SO Line Driver on
the rising edge of the SCLK signal. It is important that the
SCLK pin be in a logic [0] state whenever the
transition. SCLK has an internal pull down (l
specified in the section of the Static Electrical Characteristics
table entitled
CS
10
33976
FUNCTIONAL DESCRIPTION
INTRODUCTION
This 33976 is a single-packaged, Serial Peripheral
Each pin is the output pin of a half bridge, designed to
These pins serve as the ground for the source of the low-
The
SCLK clocks the Internal Shift registers of the 33976
is logic [1], signals at the SCLK and SI pins are ignored
CS
CS
is logic [0]. When
pin enables communication with the master
I/O, which is found on page 6.
CONTROL
CS
UP
. The output driver on the SO pin is enabled
CS
) connected to the pin, as specified in the
will only be transitioned from a logic [1]
I/O, which is found on page 6. When
CS
is logic high, signals at the
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
DWN
CS
), as
makes any
CS
has an
INTRODUCTION
to an MMT-licensed AFIC 6405 or a Switec MS-X15.xxx
motor.
systems requiring distributed and flexible step motor gauge
driving. The device also eases the transition to step motors
from air core motors by emulating the air core pointer
movement with little additional processor bandwidth
utilization.
and SO is tri-stated (high impedance). Refer to the data
transfer timing diagrams in
SERIAL OUTPUT (SO)
register. The Status register bits are the first 16 bits shifted
out. Those bits are followed by the message bits clocked in
FIFO, when the device is in a daisy chain connection or being
sent words that are multiples of 16 bits. Data is shifted on the
rising edge of the SCLK signal. The SO pin will remain in a
high impedance state until the
state.
SERIAL INPUT (SI)
is read on the falling edge of SCLK. A 16-bit stream of serial
data is required on the SI pin, beginning with the most
significant bit (MSB). Messages that are not multiples of 16
bits (e.g., daisy chained device messages) are ignored. After
transmitting a 16-bit word, the
(logic [1]) before transmitting a new word. SI information is
ignored when
MULTIPLEXED OUTPUT (RTZ)
during a Return to Zero (RTZ) event.
VOLTAGE (V
supplies.
RESET (RST)
sleep state, the RST pin is driven to a logic [0]. A logic [0] on
the
state. This input has an internal active pull-up.
The 33976 is ideal for use in automotive instrumentation
The SO data pin is a tri-stateable output from the Shift
The SI pin is the input of the SPI. Serial input information
This is a multiplexed output pin for the non-driven coil,
This SPI and logic power supply input will work with 5.0 V
If the master decides to reset the device or place it into a
RST
pin will force all internal logic to the known default
CS
DD
is in a logic high state.
)
Analog Integrated Circuit Device Data
Figure 6
CS
CS
pin must be de-asserted
pin is put into a logic low
Freescale Semiconductor
and
Figure 7
on
page
12.