mc33976 Freescale Semiconductor, Inc, mc33976 Datasheet - Page 13

• Manufacturer Part Number: mc33976
• Description: Dual Gauge Driver With Configurable Response Time
• Manufacturer: Freescale Semiconductor, Inc

DATA INPUT
the SCLK clock. The SCLK clock pulses exactly 16 times only
inside the transmission windows (
the time the
the Input Shift register are transferred to the appropriate
internal register addressed in bits 15:13. The minimum time
CS
specified in the
Static Electrical Characteristics, found on page 6. It must be
long enough so the internal clock is able to capture the data
microcontroller via the 16-bit SPI protocol specified below.
The device is controlled by the microprocessor and reports
back status information via the SPI. This section provides a
detailed description of all registers accessible via serial
interface. The various registers control the behavior of this
device.
MSB (D15) and ending with the LSB (D0). Multiple messages
can be transmitted in succession to accommodate those
applications where daisy chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of
16 bits. Data is transferred through daisy-chained devices, as
illustrated in
in a message smaller than 16 bits wide, it is ignored.
configure the device, control the state of the four H-bridge
outputs, and determine the type of status information that is
clocked back to the master. The registers are addressed via
D15:D13 of the incoming SPI word.
Table 6. Module Memory Map
Analog Integrated Circuit Device Data
Freescale Semiconductor
Address
[15:13]
The Input Shift register captures data at the falling edge of
The 33976 device is capable of interfacing directly with a
A message is transmitted by the master beginning with the
Table 6
should be kept high depends on the internal clock speed,
000
001
010
011
100
101
110
111
lists the seven registers the 33976 uses to
Power, Enable, Calibration,
Maximum Velocity Register
CS
and Configuration Register
Figure
Gauge 0 Position Register
Gauge 1 Position Register
Ramp Selection Register
Configuration Register
Return to 0 Register
signal goes to logic [1] again, the contents of
SPI INTERFACE TIMING
Reserved for Test
Return to 0
7, page 12. If an attempt is made to latch
Register
COMMUNICATION MEMORY MAPS AND REGISTER DESCRIPTIONS
CS
in a logic [0] state). By
RMPSELR
PECCR
POS0R
POS1R
RTZCR
Name
VELR
RTZR
LOGIC COMMANDS AND REGISTERS
(17)
–
section of the
See Page
Page 13
Page 15
Page 16
Page 16
Page 16
Page 17
Page 19
–
from the Input Shift register and transfer it to the internal
registers.
DATA OUTPUT
logic [0], the contents of the selected Status Word register
are transferred to the Output Shift register. The first 16 bits
clocked out are the status bits. If data continues to clock in
before the
shift out the data previously clocked in FIFO after the
transitioned to logic [0].
MODULE MEMORY MAP
by the three MSBs of the 16-bit word received serially.
Functions to be controlled include:
REGISTER DESCRIPTIONS
addresses, and their impact on device operation.
Address 000 — Power, Enable, Calibration, and
Configuration Register (PECCR)
Register is illustrated in
33976 using this register allows the master to
(1) independently enable or disable the output drivers of the
two-gauge controllers, (2) calibrate the internal clock,
(3) disable the air core emulation, (4) select the direction of
the pointer movement during pointer positioning and zeroing,
(5) configure the device for the desired status information to
At the first rising edge of the SCLK clock, with
Various registers of the 33976 SPI module are addressed
• Individual gauge drive enabling
• Power-up/down
• Internal clock calibration
• Gauge pointer position and velocity
• Gauge pointer zeroing
• Air core motor movement emulation
• Status information
Status reporting includes:
• Individual gauge overtemperature condition
• Battery overvoltage
• Battery undervoltage
• Pointer zeroing status
• Internal clock status
• Confirmation of coil output changes that should result in
• Real time pointer position information
• Real time pointer velocity step information
• Pointer movement direction
• Command pointer position status
• RTZ accumulator value
The following section describes the registers, their
The Power, Enable, Calibration, and Configuration
pointer movement
CS
transitions to a logic [1], the device begins to
LOGIC COMMANDS AND REGISTERS
Table
FUNCTIONAL DEVICE OPERATION
7, page 14. A write to the
CS
at
CS
33976
first
13