mc33596 Freescale Semiconductor, Inc, mc33596 Datasheet - Page 13

• Manufacturer Part Number: mc33596
• Description: Pll Tuned Uhf Receiver For Data Transfer Applications
• Manufacturer: Freescale Semiconductor, Inc

00h CONFIG1-A
Reset Value
01h CONFIG2-A
Reset Value
02h CONFIG3-A
Reset Value
03h COMMAND-A
Reset Value
04h F1-A
Reset Value
05h F2-A
Reset Value
Bit Name
Bit Name
Bit Name
Bit Name
Bit Name
Bit Name
0 = 304–434
1 = 315–916
0 =
1 = Adaptive
0 = 0.5–1 kHz 0.5–2 kHz
1 = 2–4 kHz
0 = AFFx OFF
1 = AFFx ON
DSREF
LOF1
Fixed
AFF1
AFFC
FSK3
Bit 7
R/W
Bit 7
R/W
Bit 7
R/W
Bit 7
R/W
Bit 7
R/W
Bit 7
R/W
F7
1
0
0
0
0
0
91 h
10 h
30 h
9 h
48 h
0 h
304–315
434–916
Friendly
1–4 kHz
–20 dB
Direct
LOF0
AFF0
FSK2
FRM
IFLA
Bit 6
R/W
Bit 6
R/W
Bit 6
R/W
Bit 6
R/W
Bit 6
R/W
Bit 6
R/W
No
F6
0
0
0
0
1
0
Unlocked
315–434
MODU
MODE
FSK1
OOK
Bit 5
Bit 5
Bit 5
OLS
RAS
Bit 5
Bit 5
Bit 5
CF1
R/W
R/W
FSK
R/W
R/W
R/W
868
RX
TX
F5
0
0
1
R
0
0
0
Bank A Registers
434–868
9.6–19.2
2.4–4.8
RSSIE
LVDS
Low V
FSK0
Bit 4
R/W
Bit 4
DR1
R/W
Bit 4
RAS
Bit 4
R/W
Bit 4
R/W
Bit 4
R/W
CF0
314
Yes
RR
No
F4
1
1
1
0
0
0
14–24 dB
Slow dec.
Fast dec.
4.8–19.2
RESET
2.4–9.6
0–8 dB
EDD
Bit 3
R/W
Bit 3
DR0
R/W
Bit 3
ILA1
R/W
Bit 3
R/W
Bit 3
R/W
Bit 3
R/W
Yes
F11
No
F3
0
0
0
1
1
0
Standby
0–14 dB
8–24 dB
Enable
RAGC
TRXE
Bit 2
R/W
Bit 2
R/W
Bit 2
ILA0
Bit 2
R/W
Bit 2
R/W
Bit 2
R/W
R/W
Yes
T/R
R/T
F10
No
SL
F1
0
0
0
0
0
0
14–24 dB
0–8 dB
LVDE
FAGC
OLA1
DME
Bit 1
R/W
Bit 1
R/W
Bit 1
R/W
Bit 1
R/W
Bit 1
R/W
Bit 1
R/W
Yes
Yes
Yes
Figure 6. Bank Registers
No
No
No
F9
F1
0
0
0
0
0
0
0–14 dB
8–24 dB
BANKS
B Bank
A Bank
CLKE
OLA0
SOE
Bit 0
R/W
Bit 0
R/W
Bit 0
R/W
Bit 0
Bit 0
R/W
Bit 0
R/W
Yes
Yes
No
No
F8
F0
R
1
0
0
1
0
0
0Dh CONFIG1-B
Reset Value
0Eh CONFIG2-B
Reset Value
0Fh CONFIG3-B
Reset Value
10h COMMAND-B
Reset Value
11h F1-B
Reset Value
12h F2-B
Reset Value
Bit Name
Bit Name
Bit Name
Bit Name
Bit Name
Bit Name
0 = 304–434
1 = 315–916
0 =
1 = Adaptive
0 = 0.5–1 kHz 0.5–2 kHz
1 = 2–4 kHz
0 = AFFx OFF
1 = AFFx ON
DSREF
LOF1
Fixed
AFF1
AFFC
FSK3
Bit 7
R/W
Bit 7
R/W
Bit 7
Bit 7
R/W
Bit 7
R/W
Bit 7
R/W
R/W
F7
1
0
0
0
0
0
91 h
10 h
30 h
9 h
4800 h
0 h
304–315
434–916
1–4 kHz
Friendly
–20 dB
Direct
LOF0
AFF0
FSK2
FRM
Bit 6
R/W
Bit 6
R/W
Bit 6
R/W
Bit 6
IFLA
R/W
Bit 6
R/W
Bit 6
R/W
No
F6
0
0
0
0
1
0
Unlocked
315–434
MODU
MODE
FSK1
OOK
RAS
Bit 5
CF1
R/W
Bit 5
R/W
FSK
Bit 5
OLS
R[A]
Bit 5
R/W
Bit 5
R/W
Bit 5
R/W
868
RX
TX
F5
0
0
1
0
0
0
Bank B Registers
434–868
9.6–19.2
2.4–4.8
RSSIE
Low V
LVDS
RR[A]
FSK0
Bit 4
R/W
Bit 4
DR1
R/W
Bit 4
RAS
Bit 4
R/W
Bit 4
R/W
Bit 4
R/W
CF0
Yes
314
No
F4
1
1
1
0
0
0
Slow dec.
14–24 dB
Fast dec.
4.8–19.2
2.4–9.6
0–8 dB
Bit 3
Bit 3
DR0
R/W
Bit 3
ILA1
R/W
Bit 3
EDD
R/W
Bit 3
R/W
Bit 3
R/W
F11
F3
—
—
—
R
0
0
0
1
1
0
0–14 dB
Standby
8–24 dB
Enable
RAGC
TRXE
ILA0
Bit 2
R/W
Bit 2
R/W
Bit 2
R/W
Bit 2
R/W
Bit 2
R/W
Bit 2
R/W
T/R
R/T
Yes
F10
SL
No
F1
0
0
0
0
0
0
14–24 dB
0–8 dB
FAGC
LVDE
OLA1
DME
Bit 1
R/W
Bit 1
R/W
Bit 1
Bit 1
R/W
Bit 1
R/W
Bit 1
R/W
Yes
Yes
R/W
Yes
No
No
No
F9
F1
0
0
0
0
0
0
0–14 dB
8–24 dB
BANKS
B Bank
A Bank
CLKE
OLA0
SOE
Bit 0
R/W
Bit 0
R[A]
Bit 0
R/W
Bit 0
R[A]
Bit 0
R/W
Bit 0
R/W
Yes
Yes
No
No
F8
F0
1
0
0
1
0
0