mc33596 Freescale Semiconductor, Inc, mc33596 Datasheet - Page 34

• Manufacturer Part Number: mc33596
• Description: Pll Tuned Uhf Receiver For Data Transfer Applications
• Manufacturer: Freescale Semiconductor, Inc

Controller
17
This section describes how the MC33596 controller executes sequences of operations, relative to the
selected mode. The controller is a finite state machine, clocked at T
Figure 27
There are three different modes: configuration, receive, and standby/LVD. Each mode is exclusive and can
be entered in different ways, as follows.
After a POR, the circuit is in state 60 (see
value.
At any time, a low level applied to CONFB forces the finite state machine into state 1, whatever the current
state. This is not always shown in state diagrams, but must always be considered.
17.1 Configuration Mode
The configuration mode is selected by the microcontroller unit (MCU) to write to the internal registers (to
configure the system) or to read them. In this mode, the SPI is a slave. The analog parts (receiver) remain
in the state (on, off) they were in prior to entering configuration mode, until a new configuration changes
them. In configuration mode, data can be neither sent nor received. As long as a low level is applied to
CONFB, the circuit stays in State 1, the only state in this mode.
Figure 28
Standby/LVD mode to configuration mode.
34
•
•
•
Power-on Reset
External signal: CONFB for configuration mode,
External signal and configuration bits: CONFB and TRXE for all other modes,
External signal and internal conditions: see
enter standby/LVD mode.
Controller
Standby/LVD Mode
(note that some branches refer to other diagrams that provide more detailed information).
and
…and SOE = 1
See
State 60
Figure 29
Figure 30
…and DME = 0
describe the two valid sequences for enabling a correct transition from
and STROBE = 0
CONFB = 1,
TRXE = 0,
CONFB = 0
…and SOE = 0
Figure 27. State Machine Overview
See
Figure 31
MC33596 Data Sheet, Rev. 3
Figure
Configuration Mode
Configuration Mode
and STROBE = 0
27) and configuration registers’ content is set to the reset
CONFB = 1,
TRXE = 1,
State 1
Figure 31
…and SOE = 1
See
and
Active Bank Change
(A to B or B to A)
Figure 32
Figure 33
digclk
. An overview is presented in
…and DME = 1
for information on how to
…and SOE = 0
See
Freescale Semiconductor
Figure 33
SPI Deselected
SPI Slave
SPI Master
Receive Mode