adm6993 Infineon Technologies Corporation, adm6993 Datasheet - Page 30

• Manufacturer Part Number: adm6993
• Description: Adm6993/x Hdlc To Fast Ethernet Converter
• Manufacturer: Infineon Technologies Corporation

3.5.3
To write data into desired EEPROM Register, write the address of the EEPROM Register.
EX. <35”1”s><01><01><00000><00100><10><001 0000000 000001 1000001000001111>
Write ADM6993/X Internal EEPROM mapping Reg.1
3.6
The ADM6993/X has an interface to HDLC. The main function is to forward Ethernet Packet from local LAN to
WAN.
3.6.1
A received packet consists of an opening flag, data bytes, a 16-bit CRC, and a closing flag. The received cycle
starts with the detection of data after the opening flag in the packet. After a flag is detected, the HDLC checks the
data bit stream for minimum (less then 62 bytes including CRC-16) and maximum (more than 1534 bytes including
CRC-16) packet lengths, zero deletion, abort characters, and idle characters. HDLC Controller will remove CRC-
16 2 byte in the received packet before writing to BUFFER.
Clocking The HDLC Controller Receiver gets data from HDLC_RXD at the positive edge of HDLC_RXCLK.
Flag Detection The HDLC supports the following received flag (01111110) sequence:
Multiple flags between packets
(.......0111111001111110......)
A flag shared as the closing and opening flags between two packets
(......Data CRC 01111110 Data......)
A shared zero between flags
(......011111101111110......)
All incoming flags are ignored and discarded by the HDLC. The first bit received, which is not a part of the flag
character, signifies the start of the packet. If a flag is received during a packet, it indicates the end of the packet.
The CRC is checked (the last two bytes of the packet), and a decision is generated to forward or not.
Zero Deletion Each bit received between the opening and closing flag is checked for zero bit insertion. A zero that
follows five contiguous ones is discarded from the incoming bit stream. HDLC is defined this feature to avoid the
occurrence of flags in user data field.
Cyclic Redundancy Check (CRC) The frame check sequence (FCS) consists of 16 bits immediately preceding
the closing flag. The 16-bit FCS detects data errors through the use of a cycle redundancy check (CRC) code. The
CRC is generated from the incoming data and compared against the received CRC (remainder), carried in the FCS
field of the packet. If the comparison does not match because of a bit error or burst error, the HDLC discards the
packet by flushing the memory buffer regions, and waits for the next packet to be received. The CRC check
polynomials are as follows:
CRC-16: X
3.6.2
A transmitted packet consists of an opening flag, data bytes, 16-bit CRC, and a closing flag. The transmitter timing
is asynchronous in relationship with the receive timing.
Clocking The HDLC Controller Transmitter send data to HDLC_TXD at the positive edge of external
HDLC_TXCLK.
Flag Generation The HDLC Controller generates either (01111110) or multiple flags (0111111001111110...),
depending on the packet data present in the BUFFER stored by LAN interface.
Data Sheet
16
Write EEPROM Register via SMI Register
HDLC Controller
HDLC Frame Receiver
+X
HDLC Frame Transmitter
12
+X
5
+1
CMD ADDRESS DATA
H
. with value 820f.
30
Function Description
Rev 1.11, 2005-11-28
ADM6993/X